cc2430_sfr.h

NanoStack is a 6lowpan IPv6 + IEEE 802.15.4 protocol stack, enabling wireless embedded and sensor ne

#define WDT_CLR0 0x10
#define WDT_EN   0x08
#define WDT_MODE 0x04
#define WDT_INT1 0x02
#define WDT_INT0 0x01

__sfr __at (0xCA)   T3CNT;

__sfr __at (0xCB)   T3CTL;
/*T3CTL bits*/
#define T3DIV2	0x80
#define T3DIV1	0x40
#define T3DIV0	0x20
#define T3START	0x10
#define T3OVFIM	0x08
#define T3CLR	0x04
#define T3MODE1	0x02
#define T3MODE0	0x01

__sfr __at (0xCC)   T3CCTL0;
/*T3CCTL0 bits*/
#define T3IM	0x40
#define T3CMP2	0x20
#define T3CMP1	0x10
#define T3CMP0	0x08
#define T3MODE	0x04
#define T3CAP1	0x02
#define T3CAP0	0x01

__sfr __at (0xCD)   T3CC0;
__sfr __at (0xCE)   T3CCTL1;
/*T3CCTL0 bits apply*/
__sfr __at (0xCF)   T3CC1;

__sfr __at (0xD0) PSW  ;
/*  PSW   */
__sbit __at (0xD0) P    ;
__sbit __at (0xD1) F1   ;
__sbit __at (0xD2) OV   ;
__sbit __at (0xD3) RS0  ;
__sbit __at (0xD4) RS1  ;
__sbit __at (0xD5) F0   ;
__sbit __at (0xD6) AC   ;
__sbit __at (0xD7) CY   ;

__sfr __at (0xD1)   DMAIRQ;
/*DMAIRQ bits*/
#define DMAIF4	0x10
#define DMAIF3	0x08
#define DMAIF2	0x04
#define DMAIF1	0x02
#define DMAIF0	0x01

__sfr __at (0xD2)   DMA1CFGL;
__sfr __at (0xD3)   DMA1CFGH;
__sfr __at (0xD4)   DMA0CFGL;
__sfr __at (0xD5)   DMA0CFGH;

__sfr __at (0xD6)   DMAARM;
/*DMAARM bits*/
#define ABORT	0x80
#define DMAARM4	0x10
#define DMAARM3	0x08
#define DMAARM2	0x04
#define DMAARM1	0x02
#define DMAARM0	0x01

__sfr __at (0xD7)   DMAREQ;
/*DMAREQ bits*/
#define DMAREQ4	0x10
#define DMAREQ3	0x08
#define DMAREQ2	0x04
#define DMAREQ1	0x02
#define DMAREQ0	0x01

__sfr __at (0xD8)   TIMIF;
/*TIMIF bits*/
#define OVFIM	0x40
#define T4CH1IF	0x20
#define T4CH0IF	0x10
#define T4OVFIF	0x08
#define T3CH1IF	0x04
#define T3CH0IF	0x02
#define T3OVFIF	0x01

__sfr __at (0xD9)   RFD;
__sfr __at (0xDA)   T1CC0L;
__sfr __at (0xDB)   T1CC0H;
__sfr __at (0xDC)   T1CC1L;
__sfr __at (0xDD)   T1CC1H;
__sfr __at (0xDE)   T1CC2L;
__sfr __at (0xDF)   T1CC2H;

__sfr __at (0xE0)   ACC;
__sfr __at (0xE1)   RFST;
__sfr __at (0xE2)   T1CNTL;
__sfr __at (0xE3)   T1CNTH;

__sfr __at (0xE4)   T1CTL;
/*T1CTL bits*/
#define CH2IF	0x80
#define CH1IF	0x40
#define CH0IF	0x20
#define OVFIF	0x10
#define T1DIV1	0x08
#define T1DIV0	0x04
#define T1MODE1	0x02
#define T1MODE0	0x01

__sfr __at (0xE5)   T1CCTL0;
/*T1CCTL0 bits*/
#define T1CPSEL	0x80
#define T1IM	0x40
#define T1CMP2	0x20
#define T1CMP1	0x10
#define T1CMP0	0x08
#define T1MODE	0x04
#define T1CAP1	0x02
#define T1CAP0	0x01

__sfr __at (0xE6)   T1CCTL1;
/*Bits defined in T1CCTL0 */
__sfr __at (0xE7)   T1CCTL2;
/*Bits defined in T1CCTL0 */
__sfr __at (0xE8)   IRCON2;
/*IRCON2 bits*/
#define WDTIF	0x10
#define P1IF	0x08
#define UTX1IF	0x04
#define UTX0IF	0x02
#define P2IF	0x01
/* IRCON 2 */ 
/*__sbit __at (0xEF) IRCON2_P1_7 ;
__sbit __at (0xEE) IRCON2_P1_6 ;
__sbit __at (0xED) IRCON2_P1_5 ;*/
__sbit __at (0xEC) IRCON2_WDTIF ;
__sbit __at (0xEB) IRCON2_P1IF ;
__sbit __at (0xEA) IRCON2_UTX1IF ;
__sbit __at (0xE9) IRCON2_UTX0IF ;
__sbit __at (0xE8) IRCON2_P2IF;


__sfr __at (0xE9)   RFIF;
/*RFIF bits*/
#define IRQ_RREG_ON	0x80
#define IRQ_TXDONE	0x40
#define IRQ_FIFOP	0x20
#define IRQ_SFD		0x10
#define IRQ_CCA		0x08
#define IRQ_CSP_WT	0x04
#define IRQ_CSP_STOP	0x02
#define IRQ_CSP_INT	0x01

__sfr __at (0xEA)   T4CNT;
__sfr __at (0xEB)   T4CTL;
/*T4CTL bits*/
#define T4DIV2	0x80
#define T4DIV1	0x40
#define T4DIV0	0x20
#define T4START	0x10
#define T4OVFIM	0x08
#define T4CLR	0x04
#define T4MODE1	0x02
#define T4MODE0	0x01

__sfr __at (0xEC)   T4CCTL0;
/*T4CCTL0 bits*/
#define T4IM	0x40
#define T4CMP2	0x20
#define T4CMP1	0x10
#define T4CMP0	0x08
#define T4MODE	0x04
#define T4CAP1	0x02
#define T4CAP0	0x01

__sfr __at (0xED)   T4CC0;
__sfr __at (0xEE)   T4CCTL1;
/*T4CCTL0 bits apply*/
__sfr __at (0xEF)   T4CC1;

__sfr __at (0xF0) B    ;
__sfr __at (0xF1)   PERCFG;
/*PERCFG bits*/
#define T1CFG	0x40
#define T3CFG	0x20
#define T4CFG	0x10
#define U1CFG	0x02
#define U0CFG	0x01

__sfr __at (0xF2)   ADCCFG;
/*ADCCFG bits*/
#define ADC7EN	0x80
#define ADC6EN	0x40
#define ADC5EN	0x20
#define ADC4EN	0x10
#define ADC3EN	0x08
#define ADC2EN	0x04
#define ADC1EN	0x02
#define ADC0EN	0x01

__sfr __at (0xF3)   P0SEL;
__sfr __at (0xF4)   P1SEL;
__sfr __at (0xF5)   P2SEL;
/*P2SEL bits*/
#define PRI3P1	0x40
#define PRI2P1	0x20
#define PRI1P1	0x10
#define PRI0P1	0x08
#define SELP2_4	0x04
#define SELP2_3	0x02
#define SELP2_0	0x01

__sfr __at (0xF6)   P1INP;

__sfr __at (0xF7)   P2INP;
/*P2INP bits*/
#define PDUP2	0x80
#define PDUP1	0x40
#define PDUP0	0x20
#define MDP2_4	0x10
#define MDP2_3	0x08
#define MDP2_2	0x04
#define MDP2_1	0x02
#define MDP2_0	0x01

__sfr __at (0xF8)   U1CSR;
__sfr __at (0xF9)   U1BUF;
__sfr __at (0xFA)   U1BAUD;
__sfr __at (0xFB)   U1UCR;
__sfr __at (0xFC)   U1GCR;
__sfr __at (0xFD)   P0DIR;
__sfr __at (0xFE)   P1DIR;

__sfr __at (0xFF)   P2DIR;
/*P2DIR bits*/
#define PRI1P0	0x80
#define PRI0P0	0x40
#define DIRP2_4	0x10
#define DIRP2_3	0x08
#define DIRP2_2	0x04
#define DIRP2_1	0x02
#define DIRP2_0	0x01

/*  IEN0  */
/*__sbit __at (0xA8) EA   ;
__sbit __at (0x99) TI   ;
__sbit __at (0x9A) RB8  ;
__sbit __at (0x9B) TB8  ;
__sbit __at (0x9C) REN  ;
__sbit __at (0x9D) SM2  ;
__sbit __at (0x9E) SM1  ;
__sbit __at (0x9F) SM0  ;*/



/* Interrupt numbers: address = (number * 8) + 3 */
/*#undef IE0_VECTOR
#undef TF0_VECTOR
#undef IE1_VECTOR
#undef TF1_VECTOR
#undef SI0_VECTOR*/

/* CC2430 interrupt vectors */
#define RFERR_VECTOR	0
#define ADC_VECTOR	1
#define URX0_VECTOR	2
#define URX1_VECTOR	3
#define ENC_VECTOR	4
#define ST_VECTOR	5
#define P2INT_VECTOR	6
#define UTX0_VECTOR	7
#define DMA_VECTOR	8
#define T1_VECTOR	9
#define T2_VECTOR	10
#define T3_VECTOR	11
#define T4_VECTOR	12
#define P0INT_VECTOR	13
#define UTX1_VECTOR	14
#define P1INT_VECTOR	15
#define RF_VECTOR	16
#define WDT_VECTOR	17

/* RF control registers*/
__xdata __at (0xDF02) MDMCTRL0H;
__xdata __at (0xDF03) MDMCTRL0L;
__xdata __at (0xDF04) MDMCTRL1H;
__xdata __at (0xDF05) MDMCTRL1L;
__xdata __at (0xDF06) RSSIH;
__xdata __at (0xDF07) RSSIL;
__xdata __at (0xDF08) SYNCWORDH;
__xdata __at (0xDF09) SYNCWORDL;
__xdata __at (0xDF0A) TXCTRLH;
__xdata __at (0xDF0B) TXCTRLL;
__xdata __at (0xDF0C) RXCTRL0H;
__xdata __at (0xDF0D) RXCTRL0L;
__xdata __at (0xDF0E) RXCTRL1H;
__xdata __at (0xDF0F) RXCTRL1L;
__xdata __at (0xDF10) FSCTRLH;
__xdata __at (0xDF11) FSCTRLL;
__xdata __at (0xDF12) CSPX;
__xdata __at (0xDF13) CSPY;
__xdata __at (0xDF14) CSPZ;
__xdata __at (0xDF15) CSPCTRL;
__xdata __at (0xDF16) CSPT;
__xdata __at (0xDF17) RFPWR;
#define ADI_RADIO_PD	0x10
#define RREG_RADIO_PD	0x08
#define RREG_DELAY_MASK 0x07

__xdata __at (0xDF20) FSMTCH;
__xdata __at (0xDF21) FSMTCL;
__xdata __at (0xDF22) MANANDH;
__xdata __at (0xDF23) MANANDL;
__xdata __at (0xDF24) MANORH;
__xdata __at (0xDF25) MANORL;
__xdata __at (0xDF26) AGCCTRLH;
__xdata __at (0xDF27) AGCCTRLL;

__xdata __at (0xDF39) FSMSTATE;
__xdata __at (0xDF3A) ADCTSTH;
__xdata __at (0xDF3B) ADCTSTL;
__xdata __at (0xDF3C) DACTSTH;
__xdata __at (0xDF3D) DACTSTL;

__xdata __at (0xDF43) IEEE_ADDR0;
__xdata __at (0xDF44) IEEE_ADDR1;
__xdata __at (0xDF45) IEEE_ADDR2;
__xdata __at (0xDF46) IEEE_ADDR3;
__xdata __at (0xDF47) IEEE_ADDR4;
__xdata __at (0xDF48) IEEE_ADDR5;
__xdata __at (0xDF49) IEEE_ADDR6;
__xdata __at (0xDF4A) IEEE_ADDR7;
__xdata __at (0xDF4B) PANIDH;
__xdata __at (0xDF4C) PANIDL;
__xdata __at (0xDF4D) SHORTADDRH;
__xdata __at (0xDF4E) SHORTADDRL;
__xdata __at (0xDF4F) IOCFG0;
__xdata __at (0xDF50) IOCFG1;
__xdata __at (0xDF51) IOCFG2;
__xdata __at (0xDF52) IOCFG3;
__xdata __at (0xDF53) RXFIFOCNT;
__xdata __at (0xDF54) FSMTC1;
#define ABORTRX_ON_SRXON 0x20
#define RX_INTERRUPTED	0x10
#define AUTO_TX2RX_OFF	0x08
#define RX2RX_TIME_OFF	0x04
#define PENDING_OR 	0x02
#define ACCEPT_ACKPKT	0x01

__xdata __at (0xDF60) CHVER;
__xdata __at (0xDF61) CHIPID;
__xdata __at (0xDF62) RFSTATUS;
#define TX_ACTIVE	0x10
#define FIFO		0x08
#define FIFOP		0x04
#define SFD		0x02
#define CCA		0x01

__xdata __at (0xDFC1)   U0BUF_SHADOW;

__xdata __at (0xDFD9) RFD_SHADOW;

__xdata __at (0xDFF9)   U1BUF_SHADOW;

#endif /*REG_CC2430*/