cc2430_sfr.h

NanoStack is a 6lowpan IPv6 + IEEE 802.15.4 protocol stack, enabling wireless embedded and sensor ne

/*
    NanoStack: MCU software and PC tools for IP-based wireless sensor networking.
		
    Copyright (C) 2006-2007 Sensinode Ltd.

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License along
    with this program; if not, write to the Free Software Foundation, Inc.,
    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

		Address:
		Sensinode Ltd.
		Teknologiantie 6	
		90570 Oulu, Finland

		E-mail:
		[e-mail]
*/


/**
 *
 * \file cc2430_sfr.h
 * \brief CC2430 registers header file for CC2430.
 *
 *  Definitions for CC2430 SFR registers.
 *   
 *	
 */

#ifndef REG_CC2430_H
#define REG_CC2430_H

/*  BYTE Register  */

__sfr __at (0x80) P0   ;
/* P0 */
__sbit __at (0x87) P0_7 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x80) P0_0 ;

__sfr __at (0x81) SP   ;
__sfr __at (0x82) DPL0  ;
__sfr __at (0x83) DPH0  ;
/*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
__sfr __at (0x84)   DPL1;
__sfr __at (0x85)   DPH1;
__sfr __at (0x86)   U0CSR;
#define U_MODE	0x80
#define U_RE	0x40
#define U_SLAVE	0x20
#define U_FE	0x10
#define U_ERR	0x08
#define U_RXB	0x04
#define	U_TXB	0x02
#define U_ACTIVE 0x01

__sfr __at (0x87) PCON ;
/*  PCON (0x87) */
#define IDLE 0x01

__sfr __at (0x88) TCON ;
/*  TCON (0x88) */
__sbit __at (0x8F) TCON_URX1IF;
/*__sbit __at (0x8E) RES;*/
__sbit __at (0x8D) TCON_ADCIF;
/*__sbit __at (0x8C) RES;*/
__sbit __at (0x8B) TCON_URX0IF;
__sbit __at (0x8A) TCON_IT1;
__sbit __at (0x89) TCON_RFERRIF;
__sbit __at (0x88) TCON_IT0;


__sfr __at (0x89)   P0IFG;
__sfr __at (0x8A)   P1IFG;
__sfr __at (0x8B)   P2IFG;
__sfr __at (0x8C)   PICTL;
/*PICTL bits*/
#define PADSC	0x40
#define P2IEN	0x20
#define P0IENH	0x10
#define P0IENL	0x08
#define P2ICON	0x04
#define P1ICON	0x02
#define P0ICON	0x01

__sfr __at (0x8D)   P1IEN;
__sfr __at (0x8F)   P0INP;

__sfr __at (0x90) P1   ;
/* P1 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;

__sfr __at (0x91)   RFIM;
__sfr __at (0x92)   DPS;
__sfr __at (0x93)   _XPAGE; /*MPAGE as paging register for sdcc*/
__sfr __at (0x94)   T2CMP;
__sfr __at (0x95)   ST0;
__sfr __at (0x96)   ST1;
__sfr __at (0x97)   ST2;
__sfr __at (0x98)   S0CON ;

__sbit __at (0x99) S0CON_ENCIF_1;
__sbit __at (0x98) S0CON_ENCIF_0;

__sfr __at (0x99)   HSRC;
__sfr __at (0x9A)   IEN2;
/*IEN2 bits*/
#define WDTIE	0x20
#define P1IE	0x10
#define UTX1IE	0x08
#define UTX0IE	0x04
#define P2IE	0x02
#define RFIE	0x01
__sfr __at (0x9B)   S1CON;
/*S1CON bits*/
#define RFIF_1	0x02
#define RFIF_0	0x01
__sfr __at (0x9C)   T2PEROF0;
__sfr __at (0x9D)   T2PEROF1;
__sfr __at (0x9E)   T2PEROF2;
/*T2PEROF2 bits*/
#define CMPIM	0x80
#define PERIM	0x40
#define OFCMPIM	0x20

#define PEROF23	0x08
#define PEROF22	0x04
#define PEROF21	0x02
#define PEROF20	0x01

__sfr __at (0x9F) FMAP;

__sfr __at (0xA0) P2   ;
/* P2 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
/*__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;*/

__sfr __at (0xA1)   T2OF0;
__sfr __at (0xA2)   T2OF1;
__sfr __at (0xA3)   T2OF2;
__sfr __at (0xA4)   T2CAPLPL;
__sfr __at (0xA5)   T2CAPHPH;
__sfr __at (0xA6)   T2TLD;
__sfr __at (0xA7)   T2THD;

__sfr __at (0xA8) IE   ;
__sfr __at (0xA8)   IEN0;
/*IEN0 bits*/
#define IEN0_EA_MASK	0x80
#define STIE	0x20
#define ENCIE	0x10
#define URX1IE	0x08
#define URX0IE	0x04
#define ADCIE	0x02
#define RFERRIE	0x01
/*  IEN0 (0xA8) */
__sbit __at (0xAF) EA;
__sbit __at (0xAF) IEN0_EA;
/*__sbit __at (0xAE) RES;*/
__sbit __at (0xAD) IEN0_STIE;
__sbit __at (0xAC) IEN0_ENCIE;
__sbit __at (0xAB) IEN0_URX1IE;
__sbit __at (0xAA) IEN0_URX0IE;
__sbit __at (0xA9) IEN0_ADCIE;
__sbit __at (0xA8) IEN0_RFERRIE;

__sfr __at (0xA9)   IP0;
/*IP0 bits*/
#define IP0_5	0x20
#define IP0_4	0x10
#define IP0_3	0x08
#define IP0_2	0x04
#define IP0_1	0x02
#define IP0_0	0x01
__sfr __at (0xAB)   FWT;
__sfr __at (0xAC)   FADDRL;
__sfr __at (0xAD)   FADDRH;

__sfr __at (0xAE)   FCTL;
#define F_BUSY	0x80
#define F_SWBSY	0x40
#define F_CONTRD 0x10
#define F_WRITE 0x02
#define F_ERASE	0x01
__sfr __at (0xAF)   FWDATA;

/*No port 3 (0xB0)*/
__sfr __at (0xB1)   ENCDI;
__sfr __at (0xB2)   ENCDO;
__sfr __at (0xB3)   ENCCS;
#define CCS_MODE2	0x40
#define CCS_MODE1	0x20
#define CCS_MODE0	0x10
#define CCS_RDY		0x08
#define CCS_CMD1	0x04
#define CCS_CMD0	0x02
#define CCS_ST		0x01
__sfr __at (0xB4)   ADCCON1;
/*ADCCON1 bits*/
#define ADEOC	0x80
#define ADST	0x40
#define ADSTS1	0x20
#define ADSTS0	0x10
#define ADRCTRL1	0x08
#define ADRCTRL0	0x04
__sfr __at (0xB5)   ADCCON2;
/*ADCCON2 bits*/
#define ADSREF1	0x80
#define ADSREF0	0x40
#define ADSDIV1	0x20
#define ADSDIV0	0x10
#define ADSCH3	0x08
#define ADSCH2	0x04
#define ADSCH1	0x02
#define ADSCH0	0x01
__sfr __at (0xB6)   ADCCON3;
/*ADCCON3 bits*/
#define ADEREF1	0x80
#define ADEREF0	0x40
#define ADEDIV1	0x20
#define ADEDIV0	0x10
#define ADECH3	0x08
#define ADECH2	0x04
#define ADECH1	0x02
#define ADECH0	0x01

__sfr __at (0xB7)   RCCTL;
#undef IP  /*this is 0xb8 in base core*/

__sfr __at (0xB8)   IEN1;
/*IEN1 bits*/
#define P0IE	0x20
#define T4IE	0x10
#define T3IE	0x08
#define T2IE	0x04
#define T1IE	0x02
#define DMAIE	0x01
/*  IEN1 (0xB8) */
/*__sbit __at (0xBF) IEN1_RES;*/
/*__sbit __at (0xBE) RES;*/
__sbit __at (0xBD) IEN1_P0IE;
__sbit __at (0xBC) IEN1_T4IE;
__sbit __at (0xBB) IEN1_T3IE;
__sbit __at (0xBA) IEN1_T2IE;
__sbit __at (0xB9) IEN1_T1IE;
__sbit __at (0xB8) IEN1_DMAIE;

__sfr __at (0xB9)   IP1;
/*IP1 bits*/
#define IP1_5	0x20
#define IP1_4	0x10
#define IP1_3	0x08
#define IP1_2	0x04
#define IP1_1	0x02
#define IP1_0	0x01

__sfr __at (0xBA)   ADCL;
__sfr __at (0xBB)   ADCH;
__sfr __at (0xBC)   RNDL;
__sfr __at (0xBD)   RNDH;

__sfr __at (0xBE)   SLEEP;
#define XOSC_STB	0x40
#define HFRC_STB	0x20
#define RST1		0x10
#define RST0		0x08
#define OSC_PD		0x04
#define SLEEP_MODE1	0x02
#define SLEEP_MODE0	0x01

__sfr __at (0xC0)   IRCON;
/*IRCON bits*/
#define STIF	0x80
#define P0IF	0x20
#define T4IF	0x10
#define T3IF	0x08
#define T2IF	0x04
#define T1IF	0x02
#define DMAIF	0x01
/* IRCON */
__sbit __at (0xC7) IRCON_STIF ;
/*__sbit __at (0x86) IRCON_6 ;*/
__sbit __at (0xC5) IRCON_P0IF;
__sbit __at (0xC4) IRCON_T4IF;
__sbit __at (0xC3) IRCON_T3IF;
__sbit __at (0xC2) IRCON_T2IF;
__sbit __at (0xC1) IRCON_T1IF;
__sbit __at (0xC0) IRCON_DMAIF;

__sfr __at (0xC1)   U0BUF;

__sfr __at (0xC2)   U0BAUD;
__sfr __at (0xC3)   T2CNF;
/*T2SEL bits*/
#define CMPIF	0x80
#define PERIF	0x40
#define OFCMPIF	0x20

#define CMSEL	0x08

#define SYNC	0x02
#define RUN	0x01

__sfr __at (0xC4)   U0UCR;
#define U_FLUSH		0x80
#define U_FLOW		0x40
#define U_D9		0x20
#define U_BIT9		0x10
#define U_PARITY	0x08
#define U_SPB		0x04
#define	U_STOP		0x02
#define U_START 	0x01

__sfr __at (0xC5)   U0GCR;
#define U_CPOL		0x80
#define U_CPHA		0x40
#define U_ORDER		0x20
#define U_BAUD_E4	0x10
#define U_BAUD_E3	0x08
#define U_BAUD_E2	0x04
#define U_BAUD_E1	0x02
#define U_BAUD_E0	0x01

__sfr __at (0xC6)   CLKCON;
#define OSC32K		0x80
#define OSC		0x40
#define TICKSPD2	0x20
#define TICKSPD1	0x10
#define TICKSPD0	0x08
#define CLKSPD		0x01

__sfr __at (0xC7)   MEMCTR;
#define MUNIF    0x40
__sfr __at (0xC8)   T2CON;

__sfr __at (0xC9)   WDCTL;
#define WDT_CLR3 0x80
#define WDT_CLR2 0x40
#define WDT_CLR1 0x20