sdram.ini

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	#define AT91C_PC6_D6       	((unsigned int) AT91C_PIO_PC6) //  
	#define AT91C_PC7_D7       	((unsigned int) AT91C_PIO_PC7) //  
	#define AT91C_PC8_D8       	((unsigned int) AT91C_PIO_PC8) //  
	#define AT91C_PC9_D9       	((unsigned int) AT91C_PIO_PC9) //  
	#define AT91C_PC10_D10      ((unsigned int) AT91C_PIO_PC10) //  
	#define AT91C_PC11_D11      ((unsigned int) AT91C_PIO_PC11) //  
	#define AT91C_PC12_D12      ((unsigned int) AT91C_PIO_PC12) //  
	#define AT91C_PC13_D13      ((unsigned int) AT91C_PIO_PC13) //  
	#define AT91C_PC14_D14      ((unsigned int) AT91C_PIO_PC14) //  
	#define AT91C_PC15_D15      ((unsigned int) AT91C_PIO_PC15) //  

	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOC,
		AT91C_PC10_D10  
			| AT91C_PC11_D11  
			| AT91C_PC12_D12  
			| AT91C_PC13_D13  
			| AT91C_PC14_D14  
			| AT91C_PC15_D15  
			| AT91C_PC0_D0    
			| AT91C_PC1_D1    
			| AT91C_PC2_D2    
			| AT91C_PC3_D3    
			| AT91C_PC4_D4    
			| AT91C_PC5_D5    
			| AT91C_PC6_D6    
			| AT91C_PC7_D7    
			| AT91C_PC8_D8    
			| AT91C_PC9_D9,
		0
	);
*/
_WDWORD(0xFFFFF800 + 0x0070, 0x0000FFFF);
_WDWORD(0xFFFFF800 + 0x0004, 0x0000FFFF);





/*===========================================================================================
	Init Sdram

	#define AT91C_SDRC_CR   ((AT91_REG *) 	0xFFFFFFB8) // (SDRC) SDRAM Controller Configuration Register
	
    // Set Control Register
	#define 	AT91C_SDRC_NC_8             ((unsigned int) 0x0) // (SDRC) 8 Bits
	
	#define 	AT91C_SDRC_NR_12            ((unsigned int) 0x1 <<  2) // (SDRC) 12 Bits
	
	#define 	AT91C_SDRC_NB_4_BANKS 		((unsigned int) 0x1 <<  4) // (SDRC) 4 banks

	#define 	AT91C_SDRC_CAS_2      		((unsigned int) 0x2 <<  5) // (SDRC) 2 cycles

	#define 	AT91C_SDRC_TWR_2    		((UINT) 0x2 <<  7) // (SDRC) Number of Write Recovery Time Cycles
	
	#define 	AT91C_SDRC_TRC_4    		((UINT) 0x4 << 11) // (SDRC) Number of RAS Cycle Time Cycles 7
	
	#define 	AT91C_SDRC_TRP_2    		((UINT) 0x2 << 15) // (SDRC) Number of RAS Precharge Time Cycles
	
	#define 	AT91C_SDRC_TRCD_3   		((UINT) 0x3 << 19) // (SDRC) Number of RAS to CAS Delay Cycles 2
	
	#define 	AT91C_SDRC_TRAS_3   		((UINT) 0x3 << 23) // (SDRC) Number of RAS Active Time Cycles 5
	
	#define 	AT91C_SDRC_TXSR_4   		((UINT) 0x4 << 27) // (SDRC) Number of Command Recovery Time Cycles 8
    
    psdrc->SDRC_CR =  AT91C_SDRC_NC_9           // 9  bits Column Addressing: 512 (A0-A8) AT91C_SDRC_NC_9
		| AT91C_SDRC_NR_13          			// 13 bits Row Addressing     8K (A0-12)  AT91C_SDRC_NR_13
		| AT91C_SDRC_CAS_2          			//  Check Table 8 for 7E(133) and 75(100) need CAS 2
		| AT91C_SDRC_NB_4_BANKS     			// 4 banks
		| AT91C_SDRC_TWR_2        
		| AT91C_SDRC_TRC_4        
		| AT91C_SDRC_TRP_2        
		| AT91C_SDRC_TRCD_3       
		| AT91C_SDRC_TRAS_3       
		| AT91C_SDRC_TXSR_4;
    // Wait time
*/
_WDWORD(0xFFFFFFB8, (0x0 << 0)	| (0x1 << 2) | (0x1 << 4) | (0x2 << 5) | (0x2 << 7)| (0x4 << 11)| (0x4 << 15)| (0x3 << 19)| (0x3 << 23)| (0x4 << 27));    	    





/*===========================================================================================
    SDRAM Init step
	
	#define		AT91C_SDRC_MR						((AT91_REG *) 	0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register
	
	#define 	AT91C_SDRC_DBW_32_BITS              ((unsigned int) 0x0 <<  4) // (SDRC) 32 Bits datas bus
	#define 	AT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus

	#define 	AT91C_SDRC_MODE_NORMAL_CMD          ((unsigned int) 0x0) // (SDRC) Normal Mode
	#define 	AT91C_SDRC_MODE_NOP_CMD             ((unsigned int) 0x1) // (SDRC) NOP Command
	#define 	AT91C_SDRC_MODE_PRCGALL_CMD         ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command
	#define 	AT91C_SDRC_MODE_LMR_CMD             ((unsigned int) 0x3) // (SDRC) Load Mode Register Command
	#define 	AT91C_SDRC_MODE_RFSH_CMD            ((unsigned int) 0x4) // (SDRC) Refresh Command

	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NOP_CMD;	// Set NOP
	*AT91C_SDRAM_BASE = 0x00000000;		                                // Perform NOP
	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | 0x00000002;		        // Set PRCHG AL
	*AT91C_SDRAM_BASE	= 0x00000000;	                                // Perform PRCHG
    // Wait time
	for (i =0; i< 10000;i++);
*/
_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x1);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x2);
_WDWORD(0x20000000, 0x0);

_sleep_(1);







/*===========================================================================================
	#define		AT91C_SDRC_MR   ((AT91_REG *) 	0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register

	#define 	AT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus
	#define 	AT91C_SDRC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRC) Refresh Command


	psdrc->SDRC_MR  = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 1st CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR
	
	psdrc->SDRC_MR  = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 2 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 3 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 4 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 5 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 6 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 7 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 8 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR
    
*/
_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);

_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x4);
_WDWORD(0x20000000, 0x0);


/*===========================================================================================
	#define		AT91C_SDRC_MR   ((AT91_REG *) 	0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register

	#define 	AT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus
	#define 	AT91C_SDRC_MODE_LMR_CMD              ((unsigned int) 0x3) // (SDRC) Load Mode Register Command

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD;	// Set LMR operation
	*(AT91C_SDRAM_BASE  + 20)= 0xcafedede;	                            // Perform LMR burst=1, lat=2
*/
_WDWORD(0xFFFFFFB0, (0x1 << 4) | 0x3);
_WDWORD(0x20000000 + 20, 0xcafedede);



/*===========================================================================================
	#define AT91C_SDRC_TR   ((AT91_REG *) 	0xFFFFFFB4) // (SDRC) SDRAM Controller Refresh Timer Register
	
	#define		AT91C_SDRC_TR_TIME			((PPHCK * 8) / 1000000)    // refresh time 384 ( 375+ 2%error)
	
    // Set Refresh Timer
	psdrc->SDRC_TR	= AT91C_SDRC_TR_TIME;
*/	
_WDWORD(0xFFFFFFB4, 375);

	


/*===========================================================================================
	#define		AT91C_SDRC_MR   ((AT91_REG *) 	0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register

	#define 	AT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus
	#define 	AT91C_SDRC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRC) Refresh Command

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS ;    // Set Normal mode // 16 bits
	*AT91C_SDRAM_BASE= 0x00000000;	              // Perform Normal mode
*/
_WDWORD(0xFFFFFFB0, 0x1 << 4);
_WDWORD(0x20000000, 0x0);





/*===========================================================================================
	Load and set pc
*/
LOAD .\SDRAM\FreqGen.axf INCREMENTAL      // Download
PC = 0x20000000;

//g, main
12

sdram.ini - 源码说明

本页面展示了「在AT91sam7SE上」中的 sdram.ini 源码文件，采用 INI 编程语言编写，共 459 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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