sdram.ini

来自「在AT91sam7SE上」· INI 代码 · 共 459 行 · 第 1/2 页

Reset;
_sleep_(100);





/*===========================================================================================
	; Disable All Interrupt
	; AIC Base Address
	AT91C_BASE_AIC  EQU     0xFFFFF000
	0x124 Interrupt Disable Command Register(2) AIC_IDCR
	0x128 Interrupt Clear Command Register(2) AIC_ICCR
*/

_WDWORD(0xFFFFF000 + 0x124, 0xFFFFFFFF);
_WDWORD(0xFFFFF000 + 0x128, 0xFFFFFFFF);




/*===========================================================================================
	Setup Main Oscillator.
	PMC base address is 0xFFFFFC00.
	0x0020 Main Oscillator Register CKGR_MOR.
*/
_sleep_(100);
_WDWORD(0xFFFFFC00 + 0x0020, 0x00004001);		// CKGR_MOR: Enable Main Oscillator
_sleep_(100);									// Wait for stable Main Oscillator





/*===========================================================================================
	Setup Pll.
	PMC base address is 0xFFFFFC00.
	0x002C PLL Register CKGR_PLLR
	PMC_PLLR_Val    EQU     0x00191C05
*/
_WDWORD(0xFFFFFC00 + 0x002C, 0x10191C05);






/*===========================================================================================
	Select Master Clock and set prescale.
	PLL & 1/2

	0x0030 Master Clock Register PMC_MCKR

	PMC_MCKR_Val    EQU     0x00000007
*/

//PLL * 1/2
_WDWORD(0xFFFFFC30, 0x00000007);        // PMC_MCKR: Switch to Main Oscillator



//PLL * 1/4
//_WDWORD(0xFFFFFC30, 0x0000000B);        // PMC_MCKR: Switch to Main Oscillator


//PLL * 1/16
//_WDWORD(0xFFFFFC30, 0x00000013);        // PMC_MCKR: Switch to Main Oscillator


//PLL * 1/32
//_WDWORD(0xFFFFFC30, 0x00000017);        // PMC_MCKR: Switch to Main Oscillator

_sleep_(100);






/*===========================================================================================
	Set EBI
	
	EBI User Interface Base Address: 0xFFFF FF80.
	0x00 Chip Select Assignment Register EBI_CSA.
	#define 	AT91C_EBI_CS1A_SDRAMC               ((unsigned int) 0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
	
    // Init the EBI for SDRAM
    AT91C_BASE_EBI -> EBI_CSA |=  AT91C_EBI_CS1A_SDRAMC;
*/
_WDWORD(0xFFFFFF80 + 0x00, 0x1 << 1);      




/*===========================================================================================
	PMC base address is 0xFFFFFC00.
	0x0010 Peripheral Clock Enable Register PMC_PCER
	#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
*/
_WDWORD(0xFFFFFC00 + 0x0010, 1 << 2);  




/*===========================================================================================
	#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
	0x0074 Peripheral B Select Register(5) PIO_BSR	
	0x0004 PIO Disable Register PIO_PDR
	
	#define AT91C_PA23_NWR1_NBS1_CFIOR_NUB	((unsigned int) AT91C_PIO_PA23) //  
	#define AT91C_PA24_SDA10				((unsigned int) AT91C_PIO_PA24)
	#define AT91C_PA25_SDCKE				((unsigned int) AT91C_PIO_PA25) //  
	#define AT91C_PA26_NCS1_SDCS			((unsigned int) AT91C_PIO_PA26) //  
	#define AT91C_PA27_SDWE					((unsigned int) AT91C_PIO_PA27) //  
	#define AT91C_PA28_CAS					((unsigned int) AT91C_PIO_PA28) //  
	#define AT91C_PA29_RAS					((unsigned int) AT91C_PIO_PA29) //  

	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOA,	
		0,					
		AT91C_PA23_NWR1_NBS1_CFIOR_NUB 
			| AT91C_PA24_SDA10          
			| AT91C_PA25_SDCKE          
			| AT91C_PA26_NCS1_SDCS       
			| AT91C_PA27_SDWE           
			| AT91C_PA28_CAS            
			| AT91C_PA29_RAS 
	); 
*/
_WDWORD(0xFFFFF400 + 0x0074, 0x3F800000);
_WDWORD(0xFFFFF400 + 0x0004, 0x3F800000);
	


/*===========================================================================================
	PMC base address is 0xFFFFFC00.
	0x0010 Peripheral Clock Enable Register PMC_PCER
	#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
*/
_WDWORD(0xFFFFFC00 + 0x0010, 1 << 3);  




	
/*===========================================================================================
	#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
	0x0074 Peripheral B Select Register(5) PIO_BSR	
	0x0004 PIO Disable Register PIO_PDR


	#define AT91C_PB0_A0_NBS0  	((unsigned int) AT91C_PIO_PB0) //  
	#define AT91C_PB1_A1_NBS2	((unsigned int) AT91C_PIO_PB1) //  
	#define AT91C_PB2_A2       	((unsigned int) AT91C_PIO_PB2) //  
	#define AT91C_PB3_A3       	((unsigned int) AT91C_PIO_PB3) //  
	#define AT91C_PB4_A4       	((unsigned int) AT91C_PIO_PB4) //  
	#define AT91C_PB5_A5		((unsigned int) AT91C_PIO_PB5) //  
	#define AT91C_PB6_A6		((unsigned int) AT91C_PIO_PB6) //  
	#define AT91C_PB7_A7		((unsigned int) AT91C_PIO_PB7) //  
	#define AT91C_PB8_A8		((unsigned int) AT91C_PIO_PB8) //  
	#define AT91C_PB9_A9		((unsigned int) AT91C_PIO_PB9) //  
	#define AT91C_PB10_A10      ((unsigned int) AT91C_PIO_PB10) //  
	#define AT91C_PB11_A11      ((unsigned int) AT91C_PIO_PB11) //  
	#define AT91C_PB12_A12      ((unsigned int) AT91C_PIO_PB12) //  
	#define AT91C_PB13_A13      ((unsigned int) AT91C_PIO_PB13) //  
	#define AT91C_PB14_A14      ((unsigned int) AT91C_PIO_PB14) //  
	#define AT91C_PB15_A15      ((unsigned int) AT91C_PIO_PB15) //  
	#define AT91C_PB16_A16_BA0  ((unsigned int) AT91C_PIO_PB16) //
	#define AT91C_PB17_A17_BA1  ((unsigned int) AT91C_PIO_PB17) //  


	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, 
		0, 
		AT91C_PB1_A1_NBS2   
			| AT91C_PB16_A16_BA0  
			| AT91C_PB0_A0_NBS0   
			| AT91C_PB2_A2        
			| AT91C_PB3_A3        
			| AT91C_PB4_A4        
			| AT91C_PB10_A10      
			| AT91C_PB5_A5        
			| AT91C_PB11_A11      
			| AT91C_PB6_A6        
			| AT91C_PB12_A12      
			| AT91C_PB7_A7        
			| AT91C_PB13_A13      
			| AT91C_PB8_A8        
			| AT91C_PB14_A14      
			| AT91C_PB9_A9        
			| AT91C_PB15_A15      
			| AT91C_PB17_A17_BA1 
	); 
	
*/
_WDWORD(0xFFFFF600 + 0x0074, 0x0003FFFF);
_WDWORD(0xFFFFF600 + 0x0004, 0x0003FFFF);
	
	
	
	
	

/*===========================================================================================
	PMC base address is 0xFFFFFC00.
	0x0010 Peripheral Clock Enable Register PMC_PCER
	#define AT91C_ID_PIOC   ((unsigned int)  4) // Parallel IO Controller C
*/
_WDWORD(0xFFFFFC00 + 0x0010, 1 << 4);  




	
/*===========================================================================================
	#define AT91C_BASE_PIOC      ((AT91PS_PIO) 	0xFFFFF800) // (PIOC) Base Address
	0x0070 Peripheral A Select Register(5) PIO_ASR
	0x0004 PIO Disable Register PIO_PDR
	
	#define AT91C_PC0_D0       	((unsigned int) AT91C_PIO_PC0) //  
	#define AT91C_PC1_D1       	((unsigned int) AT91C_PIO_PC1) //  
	#define AT91C_PC2_D2       	((unsigned int) AT91C_PIO_PC2) //  
	#define AT91C_PC3_D3       	((unsigned int) AT91C_PIO_PC3) //  
	#define AT91C_PC4_D4       	((unsigned int) AT91C_PIO_PC4) //  
	#define AT91C_PC5_D5       	((unsigned int) AT91C_PIO_PC5) //