adddiv2.vhd

附录 光盘说明 本书附赠的光盘包括各章节实例的设计工程与源码

-- 加法器除2模块 --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity adddiv2 is 
  port(
	indata1								   : in  std_logic_vector(15 downto 0);
	indata2								   : in  std_logic_vector(15 downto 0);
	outdata                                : out std_logic_vector(15 downto 0)
	   );
end adddiv2;
architecture behv of adddiv2 is
  signal symbol1		: std_logic;
  signal symbol2		: std_logic;
  signal indata1_temp	: std_logic_vector(16 downto 0);
  signal indata2_temp	: std_logic_vector(16 downto 0);
  signal result_temp	: std_logic_vector(16 downto 0);
  COMPONENT rd_lpm_add_sub0
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
	 );
  END COMPONENT;
begin
	symbol1<=indata1(15);
	symbol2<=indata2(15);
	indata1_temp(16)<=symbol1;
	indata2_temp(16)<=symbol2;
	indata1_temp(15 downto 0)<=indata1(15 downto 0);
	indata2_temp(15 downto 0)<=indata2(15 downto 0);
lpm_add_sub0_component:  rd_lpm_add_sub0
	PORT MAP
	  (
		dataa => indata1_temp,
		datab => indata2_temp,
		result => result_temp
	   );
	outdata<=result_temp(16 downto 1);
end behv;