📄 generator.map.rpt
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+---------------------------------------------+-------+
; Total logic elements ; 61 ;
; -- Combinational with no register ; 35 ;
; -- Register only ; 12 ;
; -- Combinational with a register ; 14 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 31 ;
; -- 3 input functions ; 8 ;
; -- 2 input functions ; 9 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 51 ;
; -- arithmetic mode ; 10 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 6 ;
; -- asynchronous clear/load mode ; 20 ;
; ; ;
; Total registers ; 26 ;
; Total logic cells in carry chains ; 12 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; CLR ;
; Maximum fan-out ; 27 ;
; Total fan-out ; 265 ;
; Average fan-out ; 3.31 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+
; |generator ; 61 (0) ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 35 (0) ; 12 (0) ; 14 (0) ; 12 (0) ; 0 (0) ; |generator ;
; |generator_acc6:U4| ; 7 (7) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; 6 (6) ; 0 (0) ; |generator|generator_acc6:U4 ;
; |generator_adder:U3| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |generator|generator_adder:U3 ;
; |generator_and2:U8| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |generator|generator_and2:U8 ;
; |generator_and2:U9| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |generator|generator_and2:U9 ;
; |generator_reg6:U1| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |generator|generator_reg6:U1 ;
; |generator_reg6:U2| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |generator|generator_reg6:U2 ;
; |generator_reg8:U7| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; |generator|generator_reg8:U7 ;
; |generator_sin:U6| ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |generator|generator_sin:U6 ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 26 ;
; Number of registers using Synchronous Clear ; 6 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 20 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 26 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |generator|generator_acc6:U4|Q[5] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Mon Dec 10 11:56:26 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off generator -c generator
Info: Found 2 design units, including 1 entities, in source file generator_acc6.vhd
Info: Found design unit 1: generator_acc6-rtl
Info: Found entity 1: generator_acc6
Info: Found 2 design units, including 1 entities, in source file generator_adder.vhd
Info: Found design unit 1: generator_adder-add_anGen_arch
Info: Found entity 1: generator_adder
Info: Found 2 design units, including 1 entities, in source file generator_mux.vhd
Info: Found design unit 1: generator_mux-mux_arch
Info: Found entity 1: generator_mux
Info: Found 2 design units, including 1 entities, in source file generator_and2.vhd
Info: Found design unit 1: generator_and2-and_anGen_arch
Info: Found entity 1: generator_and2
Info: Found 2 design units, including 1 entities, in source file generator_sin.vhd
Info: Found design unit 1: generator_sin-sin_arch
Info: Found entity 1: generator_sin
Info: Found 2 design units, including 1 entities, in source file generator_reg6.vhd
Info: Found design unit 1: generator_reg6-reg_arch6
Info: Found entity 1: generator_reg6
Info: Found 2 design units, including 1 entities, in source file generator_reg8.vhd
Info: Found design unit 1: generator_reg8-reg_arch8
Info: Found entity 1: generator_reg8
Warning: Can't analyze file -- file F:/复件 tijiao/程序及软件/cht05/s05p04p01/generator.vhd is missing
Warning: Using design file generator.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: generator-generator_arch
Info: Found entity 1: generator
Info: Elaborating entity "generator" for the top level hierarchy
Info: Elaborating entity "generator_reg6" for hierarchy "generator_reg6:U1"
Info: Elaborating entity "generator_sin" for hierarchy "generator_sin:U6"
Info: Elaborating entity "generator_adder" for hierarchy "generator_adder:U3"
Info: Elaborating entity "generator_acc6" for hierarchy "generator_acc6:U4"
Info: Elaborating entity "generator_reg8" for hierarchy "generator_reg8:U7"
Info: Elaborating entity "generator_and2" for hierarchy "generator_and2:U8"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
Warning: Converting TRI node "generator_sin:U6|Q[0]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[1]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[2]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[3]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[4]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[5]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[6]" that feeds logic to a wire
Warning: Converting TRI node "generator_sin:U6|Q[7]" that feeds logic to a wire
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Allocated 140 megabytes of memory during processing
Info: Processing ended: Mon Dec 10 11:56:31 2007
Info: Elapsed time: 00:00:05
Info: *******************************************************************
Info: Running Quartus II Partition Merge
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Mon Dec 10 11:56:31 2007
Info: Implemented 80 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 8 output pins
Info: Implemented 61 logic cells
Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Dec 10 11:56:31 2007
Info: Elapsed time: 00:00:00
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