generator.tan.rpt

附录 光盘说明 本书附赠的光盘包括各章节实例的设计工程与源码

; N/A           ; None        ; -3.283 ns ; CE      ; generator_reg8:U7|TEMP_Q_1[3] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[0] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -3.285 ns ; CE      ; generator_reg6:U1|TEMP_Q_0[2] ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[4]        ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[1]        ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[0]        ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[5]        ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[3]        ; CLK      ;
; N/A           ; None        ; -3.790 ns ; CE      ; generator_acc6:U4|Q[2]        ; CLK      ;
; N/A           ; None        ; -3.919 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -3.919 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -3.919 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -4.120 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[4] ; CLK      ;
; N/A           ; None        ; -4.120 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[3] ; CLK      ;
; N/A           ; None        ; -4.120 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[5] ; CLK      ;
; N/A           ; None        ; -4.128 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -4.128 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[0] ; CLK      ;
; N/A           ; None        ; -4.128 ns ; FR      ; generator_reg6:U2|TEMP_Q_0[2] ; CLK      ;
; N/A           ; None        ; -4.329 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[1] ; CLK      ;
; N/A           ; None        ; -4.329 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[0] ; CLK      ;
; N/A           ; None        ; -4.329 ns ; CE      ; generator_reg6:U2|TEMP_Q_0[2] ; CLK      ;
+---------------+-------------+-----------+---------+-------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 10 11:57:02 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off generator -c generator --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 230.31 MHz between source register "generator_acc6:U4|Q[0]" and destination register "generator_reg8:U7|TEMP_Q_1[0]" (period= 4.342 ns)
    Info: + Longest register to register delay is 4.177 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y17_N1; Fanout = 3; REG Node = 'generator_acc6:U4|Q[0]'
        Info: 2: + IC(0.542 ns) + CELL(0.451 ns) = 0.993 ns; Loc. = LC_X8_Y17_N1; Fanout = 2; COMB Node = 'generator_adder:U3|Q[0]~40COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 1.053 ns; Loc. = LC_X8_Y17_N2; Fanout = 2; COMB Node = 'generator_adder:U3|Q[1]~34COUT1'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 1.113 ns; Loc. = LC_X8_Y17_N3; Fanout = 2; COMB Node = 'generator_adder:U3|Q[2]~38COUT1'
        Info: 5: + IC(0.000 ns) + CELL(0.118 ns) = 1.231 ns; Loc. = LC_X8_Y17_N4; Fanout = 2; COMB Node = 'generator_adder:U3|Q[3]~42'
        Info: 6: + IC(0.000 ns) + CELL(0.449 ns) = 1.680 ns; Loc. = LC_X8_Y17_N6; Fanout = 24; COMB Node = 'generator_adder:U3|Q[5]~35'
        Info: 7: + IC(1.127 ns) + CELL(0.183 ns) = 2.990 ns; Loc. = LC_X7_Y18_N1; Fanout = 2; COMB Node = 'generator_sin:U6|Mux7~151'
        Info: 8: + IC(0.344 ns) + CELL(0.183 ns) = 3.517 ns; Loc. = LC_X7_Y18_N5; Fanout = 1; COMB Node = 'generator_sin:U6|Mux7~152'
        Info: 9: + IC(0.341 ns) + CELL(0.319 ns) = 4.177 ns; Loc. = LC_X7_Y18_N0; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[0]'
        Info: Total cell delay = 1.823 ns ( 43.64 % )
        Info: Total interconnect delay = 2.354 ns ( 56.36 % )
    Info: - Smallest clock skew is 0.001 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.061 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X7_Y18_N0; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[0]'
            Info: Total cell delay = 1.370 ns ( 44.76 % )
            Info: Total interconnect delay = 1.691 ns ( 55.24 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.060 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N1; Fanout = 3; REG Node = 'generator_acc6:U4|Q[0]'
            Info: Total cell delay = 1.370 ns ( 44.77 % )
            Info: Total interconnect delay = 1.690 ns ( 55.23 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "generator_reg6:U2|TEMP_Q_0[1]" (data pin = "CE", clock pin = "CLK") is 4.439 ns
    Info: + Longest pin to register delay is 7.489 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C21; Fanout = 11; PIN Node = 'CE'
        Info: 2: + IC(4.154 ns) + CELL(0.366 ns) = 5.607 ns; Loc. = LC_X7_Y19_N2; Fanout = 6; COMB Node = 'generator_and2:U8|O'
        Info: 3: + IC(1.177 ns) + CELL(0.705 ns) = 7.489 ns; Loc. = LC_X9_Y17_N7; Fanout = 3; REG Node = 'generator_reg6:U2|TEMP_Q_0[1]'
        Info: Total cell delay = 2.158 ns ( 28.82 % )
        Info: Total interconnect delay = 5.331 ns ( 71.18 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.060 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N7; Fanout = 3; REG Node = 'generator_reg6:U2|TEMP_Q_0[1]'
        Info: Total cell delay = 1.370 ns ( 44.77 % )
        Info: Total interconnect delay = 1.690 ns ( 55.23 % )
Info: tco from clock "CLK" to destination pin "Q[1]" through register "generator_reg8:U7|TEMP_Q_1[1]" is 7.349 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.061 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X7_Y18_N8; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[1]'
        Info: Total cell delay = 1.370 ns ( 44.76 % )
        Info: Total interconnect delay = 1.691 ns ( 55.24 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.132 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y18_N8; Fanout = 1; REG Node = 'generator_reg8:U7|TEMP_Q_1[1]'
        Info: 2: + IC(1.756 ns) + CELL(2.376 ns) = 4.132 ns; Loc. = PIN_N22; Fanout = 0; PIN Node = 'Q[1]'
        Info: Total cell delay = 2.376 ns ( 57.50 % )
        Info: Total interconnect delay = 1.756 ns ( 42.50 % )
Info: th for register "generator_acc6:U4|Q[4]" (data pin = "CLR", clock pin = "CLK") is -0.436 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.060 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(1.690 ns) + CELL(0.542 ns) = 3.060 ns; Loc. = LC_X9_Y17_N5; Fanout = 3; REG Node = 'generator_acc6:U4|Q[4]'
        Info: Total cell delay = 1.370 ns ( 44.77 % )
        Info: Total interconnect delay = 1.690 ns ( 55.23 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 3.596 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_R27; Fanout = 27; PIN Node = 'CLR'
        Info: 2: + IC(2.110 ns) + CELL(0.761 ns) = 3.596 ns; Loc. = LC_X9_Y17_N5; Fanout = 3; REG Node = 'generator_acc6:U4|Q[4]'
        Info: Total cell delay = 1.486 ns ( 41.32 % )
        Info: Total interconnect delay = 2.110 ns ( 58.68 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Mon Dec 10 11:57:02 2007
    Info: Elapsed time: 00:00:00