generator.tan.rpt

附录 光盘说明 本书附赠的光盘包括各章节实例的设计工程与源码

Classic Timing Analyzer report for generator
Mon Dec 10 11:57:02 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                        ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                          ; To                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.439 ns                         ; CE                            ; generator_reg6:U2|TEMP_Q_0[2] ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.349 ns                         ; generator_reg8:U7|TEMP_Q_1[1] ; Q[1]                          ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.436 ns                        ; CLR                           ; generator_acc6:U4|Q[2]        ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 230.31 MHz ( period = 4.342 ns ) ; generator_acc6:U4|Q[0]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                               ;                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------+-------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F780C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                 ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                          ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 230.31 MHz ( period = 4.342 ns )               ; generator_acc6:U4|Q[0]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.177 ns                ;
; N/A   ; 233.48 MHz ( period = 4.283 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.118 ns                ;
; N/A   ; 235.35 MHz ( period = 4.249 ns )               ; generator_reg6:U1|TEMP_Q_0[0] ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.084 ns                ;
; N/A   ; 236.35 MHz ( period = 4.231 ns )               ; generator_acc6:U4|Q[2]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.066 ns                ;
; N/A   ; 239.52 MHz ( period = 4.175 ns )               ; generator_acc6:U4|Q[1]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.010 ns                ;
; N/A   ; 239.75 MHz ( period = 4.171 ns )               ; generator_acc6:U4|Q[3]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 4.006 ns                ;
; N/A   ; 242.72 MHz ( period = 4.120 ns )               ; generator_reg6:U1|TEMP_Q_0[2] ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 3.955 ns                ;
; N/A   ; 245.82 MHz ( period = 4.068 ns )               ; generator_acc6:U4|Q[0]        ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 3.903 ns                ;
; N/A   ; 245.88 MHz ( period = 4.067 ns )               ; generator_reg6:U1|TEMP_Q_0[3] ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 3.902 ns                ;
; N/A   ; 246.06 MHz ( period = 4.064 ns )               ; generator_acc6:U4|Q[0]        ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 3.899 ns                ;
; N/A   ; 248.88 MHz ( period = 4.018 ns )               ; generator_acc6:U4|Q[0]        ; generator_reg8:U7|TEMP_Q_1[2] ; CLK        ; CLK      ; None                        ; None                      ; 3.853 ns                ;
; N/A   ; 249.31 MHz ( period = 4.011 ns )               ; generator_acc6:U4|Q[4]        ; generator_reg8:U7|TEMP_Q_1[0] ; CLK        ; CLK      ; None                        ; None                      ; 3.846 ns                ;
; N/A   ; 249.44 MHz ( period = 4.009 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 3.844 ns                ;
; N/A   ; 249.81 MHz ( period = 4.003 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 3.838 ns                ;
; N/A   ; 251.57 MHz ( period = 3.975 ns )               ; generator_reg6:U1|TEMP_Q_0[0] ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 3.810 ns                ;
; N/A   ; 252.53 MHz ( period = 3.960 ns )               ; generator_reg6:U1|TEMP_Q_0[0] ; generator_reg8:U7|TEMP_Q_1[1] ; CLK        ; CLK      ; None                        ; None                      ; 3.795 ns                ;
; N/A   ; 252.59 MHz ( period = 3.959 ns )               ; generator_reg6:U1|TEMP_Q_0[1] ; generator_reg8:U7|TEMP_Q_1[2] ; CLK        ; CLK      ; None                        ; None                      ; 3.794 ns                ;
; N/A   ; 252.72 MHz ( period = 3.957 ns )               ; generator_acc6:U4|Q[2]        ; generator_reg8:U7|TEMP_Q_1[5] ; CLK        ; CLK      ; None                        ; None                      ; 3.792 ns                ;