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A51 MACRO ASSEMBLER EX 12/09/2008 17:19:28 PAGE 1
MACRO ASSEMBLER A51 V7.04a
OBJECT MODULE PLACED IN EX.OBJ
ASSEMBLER INVOKED BY: C:\SiLabs\MCU\IDEfiles\C51\BIN\a51.exe EX.ASM XR GEN DB EP NOMOD51
LOC OBJ LINE SOURCE
1 ;-----------------------------------------------------------
2 ; Exercice 14 Chronometre
3 ;-----------------------------------------------------------
4 ;$include (c8051f000.inc) ;Include register definition file.
+1 5 ;-----------------------------------------------------------------------------
+1 6 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
+1 7 ; All rights reserved.
+1 8 ;
+1 9 ;
+1 10 ; FILE NAME : C8051F000.INC
+1 11 ; TARGET MCUs : C8051F000, 'F001, 'F002, 'F010, 'F011, 'F012, 'F005, 'F006,
+1 12 ; 'F007, 'F015, 'F016 and 'F017
+1 13 ; DESCRIPTION : Register/bit definitions for the C8051F0xx product family.
+1 14 ;
+1 15 ; REVISION 1.9
+1 16 ;
+1 17 ;-----------------------------------------------------------------------------
+1 18 ;REGISTER DEFINITIONS
+1 19 ;
0080 +1 20 P0 DATA 080H ; PORT 0
0081 +1 21 SP DATA 081H ; STACK POINTER
0082 +1 22 DPL DATA 082H ; DATA POINTER - LOW BYTE
0083 +1 23 DPH DATA 083H ; DATA POINTER - HIGH BYTE
0087 +1 24 PCON DATA 087H ; POWER CONTROL
0088 +1 25 TCON DATA 088H ; TIMER CONTROL
0089 +1 26 TMOD DATA 089H ; TIMER MODE
008A +1 27 TL0 DATA 08AH ; TIMER 0 - LOW BYTE
008B +1 28 TL1 DATA 08BH ; TIMER 1 - LOW BYTE
008C +1 29 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
008D +1 30 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
008E +1 31 CKCON DATA 08EH ; CLOCK CONTROL
008F +1 32 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
0090 +1 33 P1 DATA 090H ; PORT 1
0091 +1 34 TMR3CN DATA 091H ; TIMER 3 CONTROL
0092 +1 35 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE
0093 +1 36 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE
0094 +1 37 TMR3L DATA 094H ; TIMER 3 - LOW BYTE
0095 +1 38 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE
0098 +1 39 SCON DATA 098H ; SERIAL PORT CONTROL
0099 +1 40 SBUF DATA 099H ; SERIAL PORT BUFFER
009A +1 41 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
009B +1 42 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA
009D +1 43 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
009E +1 44 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL
009F +1 45 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL
00A0 +1 46 P2 DATA 0A0H ; PORT 2
00A4 +1 47 PRT0CF DATA 0A4H ; PORT 0 CONFIGURATION
00A5 +1 48 PRT1CF DATA 0A5H ; PORT 1 CONFIGURATION
00A6 +1 49 PRT2CF DATA 0A6H ; PORT 2 CONFIGURATION
00A7 +1 50 PRT3CF DATA 0A7H ; PORT 3 CONFIGURATION
00A8 +1 51 IE DATA 0A8H ; INTERRUPT ENABLE
00AD +1 52 PRT1IF DATA 0ADH ; PORT 1 EXTERNAL INTERRUPT FLAGS
00AF +1 53 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL
00B0 +1 54 P3 DATA 0B0H ; PORT 3
00B1 +1 55 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
00B2 +1 56 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
00B6 +1 57 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER
00B7 +1 58 FLACL DATA 0B7H ; FLASH ACESS LIMIT
A51 MACRO ASSEMBLER EX 12/09/2008 17:19:28 PAGE 2
00B8 +1 59 IP DATA 0B8H ; INTERRUPT PRIORITY
00BA +1 60 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION
00BB +1 61 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION
00BC +1 62 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION
00BE +1 63 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE
00BF +1 64 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE
00C0 +1 65 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL
00C1 +1 66 SMB0STA DATA 0C1H ; SMBUS 0 STATUS
00C2 +1 67 SMB0DAT DATA 0C2H ; SMBUS 0 DATA
00C3 +1 68 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS
00C4 +1 69 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
00C5 +1 70 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
00C6 +1 71 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE
00C7 +1 72 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
00C8 +1 73 T2CON DATA 0C8H ; TIMER 2 CONTROL
00CA +1 74 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE
00CB +1 75 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
00CC +1 76 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE
00CD +1 77 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE
00CF +1 78 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE
00D0 +1 79 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 80 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
00D2 +1 81 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE
00D3 +1 82 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE
00D4 +1 83 DAC0CN DATA 0D4H ; DAC 0 CONTROL
00D5 +1 84 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE
00D6 +1 85 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE
00D7 +1 86 DAC1CN DATA 0D7H ; DAC 1 CONTROL
00D8 +1 87 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL
00D9 +1 88 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE
00DA +1 89 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0
00DB +1 90 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1
00DC +1 91 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2
00DD +1 92 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3
00DE +1 93 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4
00E0 +1 94 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 95 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
00E2 +1 96 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
00E3 +1 97 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
00E6 +1 98 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
00E7 +1 99 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
00E8 +1 100 ADC0CN DATA 0E8H ; ADC 0 CONTROL
00E9 +1 101 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE
00EA +1 102 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
00EB +1 103 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
00EC +1 104 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
00ED +1 105 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
00EE +1 106 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
00EF +1 107 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 108 B DATA 0F0H ; B REGISTER
00F6 +1 109 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
00F7 +1 110 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
00F8 +1 111 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL
00F9 +1 112 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE
00FA +1 113 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
00FB +1 114 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
00FC +1 115 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
00FD +1 116 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
00FE +1 117 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
00FF +1 118 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
+1 119 ;
+1 120 ;------------------------------------------------------------------------------
+1 121 ;BIT DEFINITIONS
+1 122 ;
+1 123 ; TCON 88H
0088 +1 124 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
A51 MACRO ASSEMBLER EX 12/09/2008 17:19:28 PAGE 3
0089 +1 125 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
008A +1 126 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
008B +1 127 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
008C +1 128 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
008D +1 129 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
008E +1 130 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
008F +1 131 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG
+1 132 ;
+1 133 ; SCON 98H
0098 +1 134 RI BIT SCON.0 ; RECEIVE INTERRUPT FLAG
0099 +1 135 TI BIT SCON.1 ; TRANSMIT INTERRUPT FLAG
009A +1 136 RB8 BIT SCON.2 ; RECEIVE BIT 8
009B +1 137 TB8 BIT SCON.3 ; TRANSMIT BIT 8
009C +1 138 REN BIT SCON.4 ; RECEIVE ENABLE
009D +1 139 SM2 BIT SCON.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
009E +1 140 SM1 BIT SCON.6 ; SERIAL MODE CONTROL BIT 1
009F +1 141 SM0 BIT SCON.7 ; SERIAL MODE CONTROL BIT 0
+1 142 ;
+1 143 ; IE A8H
00A8 +1 144 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
00A9 +1 145 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
00AA +1 146 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
00AB +1 147 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
00AC +1 148 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
00AD +1 149 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
00AF +1 150 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
+1 151 ;
+1 152 ; IP B8H
00B8 +1 153 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
00B9 +1 154 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00BA +1 155 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00BB +1 156 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00BC +1 157 PS BIT IP.4 ; SERIAL PORT PRIORITY
00BD +1 158 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 159 ;
+1 160 ; SMB0CN C0H
00C0 +1 161 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C1 +1 162 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C2 +1 163 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C3 +1 164 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C4 +1 165 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C5 +1 166 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
00C6 +1 167 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
+1 168 ;
+1 169 ; T2CON C8H
00C8 +1 170 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
00C9 +1 171 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
00CA +1 172 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00CB +1 173 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00CC +1 174 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00CD +1 175 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00CE +1 176 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
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