header.h

linux下的pci设备浏览工具

#define PCI_HT_IDC_IDX		2	/* Index Register */
#define PCI_HT_IDC_DATA		4	/* Data Register */
#define PCI_HT_IDC_SIZEOF	8

					/* Register indices */
#define  PCI_HT_IDC_IDX_LINT	0x01	/* Last Interrupt Register */
#define   PCI_HT_IDC_LINT	0x00ff0000 /* Last interrupt definition */
#define  PCI_HT_IDC_IDX_IDR	0x10	/* Interrupt Definition Registers */
					/* Low part (at index) */
#define   PCI_HT_IDC_IDR_MASK	0x10000001 /* Mask */
#define   PCI_HT_IDC_IDR_POL	0x10000002 /* Polarity */
#define   PCI_HT_IDC_IDR_II_2	0x1000001c /* IntrInfo[4:2]: Message Type */
#define   PCI_HT_IDC_IDR_II_5	0x10000020 /* IntrInfo[5]: Request EOI */
#define   PCI_HT_IDC_IDR_II_6	0x00ffffc0 /* IntrInfo[23:6] */
#define   PCI_HT_IDC_IDR_II_24	0xff000000 /* IntrInfo[31:24] */
					/* High part (at index + 1) */
#define   PCI_HT_IDC_IDR_II_32	0x00ffffff /* IntrInfo[55:32] */
#define   PCI_HT_IDC_IDR_PASSPW	0x40000000 /* PassPW setting for messages */
#define   PCI_HT_IDC_IDR_WEOI	0x80000000 /* Waiting for EOI */

/* HyperTransport: Revision ID */
#define PCI_HT_RID_RID		2	/* Revision Register */
#define PCI_HT_RID_SIZEOF	4

/* HyperTransport: UnitID Clumping */
#define PCI_HT_UIDC_CS		4	/* Clumping Support Register */
#define PCI_HT_UIDC_CE		8	/* Clumping Enable Register */
#define PCI_HT_UIDC_SIZEOF	12

/* HyperTransport: Extended Configuration Space Access */
#define PCI_HT_ECSA_ADDR	4	/* Configuration Address Register */
#define  PCI_HT_ECSA_ADDR_REG	0x00000ffc /* Register */
#define  PCI_HT_ECSA_ADDR_FUN	0x00007000 /* Function */
#define  PCI_HT_ECSA_ADDR_DEV	0x000f1000 /* Device */
#define  PCI_HT_ECSA_ADDR_BUS	0x0ff00000 /* Bus Number */
#define  PCI_HT_ECSA_ADDR_TYPE	0x10000000 /* Access Type */
#define PCI_HT_ECSA_DATA	8	/* Configuration Data Register */
#define PCI_HT_ECSA_SIZEOF	12

/* HyperTransport: Address Mapping */
#define PCI_HT_AM_CMD		2	/* Command Register */
#define  PCI_HT_AM_CMD_NDMA	0x000f	/* Number of DMA Mappings */
#define  PCI_HT_AM_CMD_IOSIZ	0x01f0	/* I/O Size */
#define  PCI_HT_AM_CMD_MT	0x0600	/* Map Type */
#define  PCI_HT_AM_CMD_MT_40B	0x0000	/* 40-bit */
#define  PCI_HT_AM_CMD_MT_64B	0x0200	/* 64-bit */

					/* Window Control Register bits */
#define  PCI_HT_AM_SBW_CTR_COMP	0x1	/* Compat */
#define  PCI_HT_AM_SBW_CTR_NCOH	0x2	/* NonCoherent */
#define  PCI_HT_AM_SBW_CTR_ISOC	0x4	/* Isochronous */
#define  PCI_HT_AM_SBW_CTR_EN	0x8	/* Enable */

/* HyperTransport: 40-bit Address Mapping */
#define PCI_HT_AM40_SBNPW	4	/* Secondary Bus Non-Prefetchable Window Register */
#define  PCI_HT_AM40_SBW_BASE	0x000fffff /* Window Base */
#define  PCI_HT_AM40_SBW_CTR	0xf0000000 /* Window Control */
#define PCI_HT_AM40_SBPW	8	/* Secondary Bus Prefetchable Window Register */
#define PCI_HT_AM40_DMA_PBASE0	12	/* DMA Window Primary Base 0 Register */
#define PCI_HT_AM40_DMA_CTR0	15	/* DMA Window Control 0 Register */
#define  PCI_HT_AM40_DMA_CTR_CTR 0xf0	/* Window Control */
#define PCI_HT_AM40_DMA_SLIM0	16	/* DMA Window Secondary Limit 0 Register */
#define PCI_HT_AM40_DMA_SBASE0	18	/* DMA Window Secondary Base 0 Register */
#define PCI_HT_AM40_SIZEOF	12	/* size is variable: 12 + 8 * NDMA */

/* HyperTransport: 64-bit Address Mapping */
#define PCI_HT_AM64_IDX		4	/* Index Register */
#define PCI_HT_AM64_DATA_LO	8	/* Data Lower Register */
#define PCI_HT_AM64_DATA_HI	12	/* Data Upper Register */
#define PCI_HT_AM64_SIZEOF	16

					/* Register indices */
#define  PCI_HT_AM64_IDX_SBNPW	0x00	/* Secondary Bus Non-Prefetchable Window Register */
#define   PCI_HT_AM64_W_BASE_LO	0xfff00000 /* Window Base Lower */
#define   PCI_HT_AM64_W_CTR	0x0000000f /* Window Control */
#define  PCI_HT_AM64_IDX_SBPW	0x01	/* Secondary Bus Prefetchable Window Register */
#define   PCI_HT_AM64_IDX_PBNPW	0x02	/* Primary Bus Non-Prefetchable Window Register */
#define   PCI_HT_AM64_IDX_DMAPB0 0x04	/* DMA Window Primary Base 0 Register */
#define   PCI_HT_AM64_IDX_DMASB0 0x05	/* DMA Window Secondary Base 0 Register */
#define   PCI_HT_AM64_IDX_DMASL0 0x06	/* DMA Window Secondary Limit 0 Register */

/* HyperTransport: MSI Mapping */
#define PCI_HT_MSIM_CMD		2	/* Command Register */
#define  PCI_HT_MSIM_CMD_EN	0x0001	/* Mapping Active */
#define  PCI_HT_MSIM_CMD_FIXD	0x0002	/* MSI Mapping Address Fixed */
#define PCI_HT_MSIM_ADDR_LO	4	/* MSI Mapping Address Lower Register */
#define PCI_HT_MSIM_ADDR_HI	8	/* MSI Mapping Address Upper Register */
#define PCI_HT_MSIM_SIZEOF	12

/* HyperTransport: DirectRoute */
#define PCI_HT_DR_CMD		2	/* Command Register */
#define  PCI_HT_DR_CMD_NDRS	0x000f	/* Number of DirectRoute Spaces */
#define  PCI_HT_DR_CMD_IDX	0x01f0	/* Index */
#define PCI_HT_DR_EN		4	/* Enable Vector Register */
#define PCI_HT_DR_DATA		8	/* Data Register */
#define PCI_HT_DR_SIZEOF	12

					/* Register indices */
#define  PCI_HT_DR_IDX_BASE_LO	0x00	/* DirectRoute Base Lower Register */
#define   PCI_HT_DR_OTNRD	0x00000001 /* Opposite to Normal Request Direction */
#define   PCI_HT_DR_BL_LO	0xffffff00 /* Base/Limit Lower */
#define  PCI_HT_DR_IDX_BASE_HI	0x01	/* DirectRoute Base Upper Register */
#define  PCI_HT_DR_IDX_LIMIT_LO	0x02	/* DirectRoute Limit Lower Register */
#define  PCI_HT_DR_IDX_LIMIT_HI	0x03	/* DirectRoute Limit Upper Register */

/* HyperTransport: VCSet */
#define PCI_HT_VCS_SUP		4	/* VCSets Supported Register */
#define PCI_HT_VCS_L1EN		5	/* Link 1 VCSets Enabled Register */
#define PCI_HT_VCS_L0EN		6	/* Link 0 VCSets Enabled Register */
#define PCI_HT_VCS_SBD		8	/* Stream Bucket Depth Register */
#define PCI_HT_VCS_SINT		9	/* Stream Interval Register */
#define PCI_HT_VCS_SSUP		10	/* Number of Streaming VCs Supported Register */
#define  PCI_HT_VCS_SSUP_0	0x00	/* Streaming VC 0 */
#define  PCI_HT_VCS_SSUP_3	0x01	/* Streaming VCs 0-3 */
#define  PCI_HT_VCS_SSUP_15	0x02	/* Streaming VCs 0-15 */
#define PCI_HT_VCS_NFCBD	12	/* Non-FC Bucket Depth Register */
#define PCI_HT_VCS_NFCINT	13	/* Non-FC Bucket Interval Register */
#define PCI_HT_VCS_SIZEOF	16

/* HyperTransport: Retry Mode */
#define PCI_HT_RM_CTR0		4	/* Control 0 Register */
#define  PCI_HT_RM_CTR_LRETEN	0x01	/* Link Retry Enable */
#define  PCI_HT_RM_CTR_FSER	0x02	/* Force Single Error */
#define  PCI_HT_RM_CTR_ROLNEN	0x04	/* Rollover Nonfatal Enable */
#define  PCI_HT_RM_CTR_FSS	0x08	/* Force Single Stomp */
#define  PCI_HT_RM_CTR_RETNEN	0x10	/* Retry Nonfatal Enable */
#define  PCI_HT_RM_CTR_RETFEN	0x20	/* Retry Fatal Enable */
#define  PCI_HT_RM_CTR_AA	0xc0	/* Allowed Attempts */
#define PCI_HT_RM_STS0		5	/* Status 0 Register */
#define  PCI_HT_RM_STS_RETSNT	0x01	/* Retry Sent */
#define  PCI_HT_RM_STS_CNTROL	0x02	/* Count Rollover */
#define  PCI_HT_RM_STS_SRCV	0x04	/* Stomp Received */
#define PCI_HT_RM_CTR1		6	/* Control 1 Register */
#define PCI_HT_RM_STS1		7	/* Status 1 Register */
#define PCI_HT_RM_CNT0		8	/* Retry Count 0 Register */
#define PCI_HT_RM_CNT1		10	/* Retry Count 1 Register */
#define PCI_HT_RM_SIZEOF	12

/* PCI Express */
#define PCI_EXP_FLAGS		0x2	/* Capabilities register */
#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIE Bridge */
#define  PCI_EXP_TYPE_ROOT_INT_EP 0x9	/* Root Complex Integrated Endpoint */
#define  PCI_EXP_TYPE_ROOT_EC 0xa	/* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
#define PCI_EXP_DEVCAP		0x4	/* Device capabilities */
#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
#define  PCI_EXP_DEVCAP_RBE	0x8000	/* Role-Based Error Reporting */
#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
#define  PCI_EXP_DEVCAP_FLRESET	0x10000000 /* Function-Level Reset */
#define PCI_EXP_DEVCTL		0x8	/* Device Control */
#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
#define  PCI_EXP_DEVCTL_RELAXED	0x0010	/* Enable Relaxed Ordering */
#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
#define  PCI_EXP_DEVCTL_NOSNOOP	0x0800	/* Enable No Snoop */
#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
#define  PCI_EXP_DEVCTL_BCRE	0x8000	/* Bridge Configuration Retry Enable */
#define  PCI_EXP_DEVCTL_FLRESET	0x8000	/* Function-Level Reset [bit shared with BCRE] */
#define PCI_EXP_DEVSTA		0xa	/* Device Status */
#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
#define PCI_EXP_LNKCAP		0xc	/* Link Capabilities */
#define  PCI_EXP_LNKCAP_SPEED	0x0000f	/* Maximum Link Speed */
#define  PCI_EXP_LNKCAP_WIDTH	0x003f0	/* Maximum Link Width */
#define  PCI_EXP_LNKCAP_ASPM	0x00c00	/* Active State Power Management */
#define  PCI_EXP_LNKCAP_L0S	0x07000	/* L0s Acceptable Latency */
#define  PCI_EXP_LNKCAP_L1	0x38000	/* L1 Acceptable Latency */
#define  PCI_EXP_LNKCAP_CLOCKPM	0x40000	/* Clock Power Management */
#define  PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
#define  PCI_EXP_LNKCAP_DLLA	0x100000 /* Data Link Layer Active Reporting */
#define  PCI_EXP_LNKCAP_LBNC	0x200000 /* Link Bandwidth Notification Capability */
#define  PCI_EXP_LNKCAP_PORT	0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL		0x10	/* Link Control */
#define  PCI_EXP_LNKCTL_ASPM	0x0003	/* ASPM Control */
#define  PCI_EXP_LNKCTL_RCB	0x0008	/* Read Completion Boundary */
#define  PCI_EXP_LNKCTL_DISABLE	0x0010	/* Link Disable */
#define  PCI_EXP_LNKCTL_RETRAIN	0x0020	/* Retrain Link */
#define  PCI_EXP_LNKCTL_CLOCK	0x0040	/* Common Clock Configuration */
#define  PCI_EXP_LNKCTL_XSYNCH	0x0080	/* Extended Synch */
#define  PCI_EXP_LNKCTL_CLOCKPM	0x0100	/* Clock Power Management */
#define  PCI_EXP_LNKCTL_HWAUTWD	0x0200	/* Hardware Autonomous Width Disable */
#define  PCI_EXP_LNKCTL_BWMIE	0x0400	/* Bandwidth Mgmt Interrupt Enable */
#define  PCI_EXP_LNKCTL_AUTBWIE	0x0800	/* Autonomous Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKSTA		0x12	/* Link Status */
#define  PCI_EXP_LNKSTA_SPEED	0x000f	/* Negotiated Link Speed */
#define  PCI_EXP_LNKSTA_WIDTH	0x03f0	/* Negotiated Link Width */
#define  PCI_EXP_LNKSTA_TR_ERR	0x0400	/* Training Error (obsolete) */
#define  PCI_EXP_LNKSTA_TRAIN	0x0800	/* Link Training */
#define  PCI_EXP_LNKSTA_SL_CLK	0x1000	/* Slot Clock Configuration */
#define  PCI_EXP_LNKSTA_DL_ACT	0x2000	/* Data Link Layer in DL_Active State */
#define  PCI_EXP_LNKSTA_BWMGMT	0x4000	/* Bandwidth Mgmt Status */
#define  PCI_EXP_LNKSTA_AUTBW	0x8000	/* Autonomous Bandwidth Mgmt Status */
#define PCI_EXP_SLTCAP		0x14	/* Slot Capabilities */
#define  PCI_EXP_SLTCAP_ATNB	0x0001	/* Attention Button Present */
#define  PCI_EXP_SLTCAP_PWRC	0x0002	/* Power Controller Present */
#define  PCI_EXP_SLTCAP_MRL	0x0004	/* MRL Sensor Present */
#define  PCI_EXP_SLTCAP_ATNI	0x0008	/* Attention Indicator Present */
#define  PCI_EXP_SLTCAP_PWRI	0x0010	/* Power Indicator Present */
#define  PCI_EXP_SLTCAP_HPS	0x0020	/* Hot-Plug Surprise */
#define  PCI_EXP_SLTCAP_HPC	0x0040	/* Hot-Plug Capable */
#define  PCI_EXP_SLTCAP_PWR_VAL	0x00007f80 /* Slot Power Limit Value */
#define  PCI_EXP_SLTCAP_PWR_SCL	0x00018000 /* Slot Power Limit Scale */
#define  PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
#define  PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
#define PCI_EXP_SLTCTL		0x18	/* Slot Control */
#define  PCI_EXP_SLTCTL_ATNB	0x0001	/* Attention Button Pressed Enable */
#define  PCI_EXP_SLTCTL_PWRF	0x0002	/* Power Fault Detected Enable */
#define  PCI_EXP_SLTCTL_MRLS	0x0004	/* MRL Sensor Changed Enable */
#define  PCI_EXP_SLTCTL_PRSD	0x0008	/* Presence Detect Changed Enable */
#define  PCI_EXP_SLTCTL_CMDC	0x0010	/* Command Completed Interrupt Enable */
#define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
#define  PCI_EXP_SLTCTL_ATNI	0x00c0	/* Attention Indicator Control */
#define  PCI_EXP_SLTCTL_PWRI	0x0300	/* Power Indicator Control */
#define  PCI_EXP_SLTCTL_PWRC	0x0400	/* Power Controller Control */
#define  PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
#define  PCI_EXP_SLTCTL_LLCHG	0x1000	/* Data Link Layer State Changed Enable */
#define PCI_EXP_SLTSTA		0x1a	/* Slot Status */
#define  PCI_EXP_SLTSTA_ATNB	0x0001	/* Attention Button Pressed */
#define  PCI_EXP_SLTSTA_PWRF	0x0002	/* Power Fault Detected */
#define  PCI_EXP_SLTSTA_MRLS	0x0004	/* MRL Sensor Changed */
#define  PCI_EXP_SLTSTA_PRSD	0x0008	/* Presence Detect Changed */
#define  PCI_EXP_SLTSTA_CMDC	0x0010	/* Command Completed */
#define  PCI_EXP_SLTSTA_MRL_ST	0x0020	/* MRL Sensor State */
#define  PCI_EXP_SLTSTA_PRES	0x0040	/* Presence Detect State */
#define  PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
#define  PCI_EXP_SLTSTA_LLCHG	0x0100	/* Data Link Layer State Changed */
#define PCI_EXP_RTCTL		0x1c	/* Root Control */
#define  PCI_EXP_RTCTL_SECEE	0x0001	/* System Error on Correctable Error */
#define  PCI_EXP_RTCTL_SENFEE	0x0002	/* System Error on Non-Fatal Error */
#define  PCI_EXP_RTCTL_SEFEE	0x0004	/* System Error on Fatal Error */
#define  PCI_EXP_RTCTL_PMEIE	0x0008	/* PME Interrupt Enable */
#define  PCI_EXP_RTCTL_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTCAP		0x1e	/* Root Capabilities */
#define  PCI_EXP_RTCAP_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTSTA		0x20	/* Root Status */
#define  PCI_EXP_RTSTA_PME_REQID   0x0000ffff /* PME Requester ID */
#define  PCI_EXP_RTSTA_PME_STATUS  0x00010000 /* PME Status */
#define  PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
#define PCI_EXP_DEVCAP2			0x24	/* Device capabilities 2 */
#define PCI_EXP_DEVCTL2			0x28	/* Device Control */
#define  PCI_EXP_DEV2_TIMEOUT_RANGE(x)	((x) & 0xf) /* Completion Timeout Ranges Supported */
#define  PCI_EXP_DEV2_TIMEOUT_VALUE(x)	((x) & 0xf) /* Completion Timeout Value */
#define  PCI_EXP_DEV2_TIMEOUT_DIS	0x0010	/* Completion Timeout Disable Supported */
#define  PCI_EXP_DEV2_ARI		0x0020	/* ARI Forwarding */
#define PCI_EXP_DEVSTA2			0x2a	/* Device Status */
#define PCI_EXP_LNKCAP2			0x2c	/* Link Capabilities */
#define PCI_EXP_LNKCTL2			0x30	/* Link Control */
#define  PCI_EXP_LNKCTL2_SPEED(x)	((x) & 0xf) /* Target Link Speed */
#define  PCI_EXP_LNKCTL2_CMPLNC		0x0010	/* Enter Compliance */
#define  PCI_EXP_LNKCTL2_SPEED_DIS	0x0020	/* Hardware Autonomous Speed Disable */
#define  PCI_EXP_LNKCTL2_DEEMPHASIS(x)	(((x) >> 6) & 1) /* Selectable De-emphasis */
#define  PCI_EXP_LNKCTL2_MARGIN(x)	(((x) >> 7) & 7) /* Transmit Margin */
#define  PCI_EXP_LNKCTL2_MOD_CMPLNC	0x0400	/* Enter Modified Compliance */
#define  PCI_EXP_LNKCTL2_CMPLNC_SOS	0x0800	/* Compliance SOS */
#define  PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
#define PCI_EXP_LNKSTA2			0x32	/* Link Status */
#define  PCI_EXP_LINKSTA2_DEEMPHASIS(x)	((x) & 1)	/* Current De-emphasis Level */
#define PCI_EXP_SLTCAP2			0x34	/* Slot Capabilities */
#define PCI_EXP_SLTCTL2			0x38	/* Slot Control */