sensordata.vhd

nios sopc上的sram调试程序

----cg--entities/SensorData/header--begin
-------------------------------------------------------------------------------
--
--		Design units	:  SensorData
--
--		Filename		:  SensorData.vhd
--
--		Created 		:
--
--		Author			:  Alexander Kramer
--
--		Description 	:
--
--		Todo			:
--
--		Dependencies	:
--
--		Library 		:
--
--		Known Errors	: 
--
-------------------------------------------------------------------------------
--		Last Changes	:
--		Author				Date			Changes
--		AK
-------------------------------------------------------------------------------
----cg--entities/SensorData/header--end

----cg--entities/SensorData/libs--begin
library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     IEEE.STD_LOGIC_UNSIGNED.ALL;
use     IEEE.STD_LOGIC_ARITH.ALL;
use     IEEE.MATH_REAL.ALL;
----cg--entities/SensorData/libs--end

entity SensorData is
  	port
	(
		--SDRAM  (Page 4)
	  	SD_DQ  : inout std_logic_vector(31 downto 0); --Data
	  	SD_A  : out std_logic_vector(12 downto 0); --Address
	  	SD_BA  : out std_logic_vector(1 downto 0); --
	  	SD_DQM  : out std_logic_vector(3 downto 0); --
	  	SD_CAS_N  : out std_logic; --
	  	SD_RAS_N  : out std_logic; --
	  	SD_WE_N  : out std_logic; --
	  	SD_CKE  : out std_logic; --
	  	SD_CS_N  : out std_logic; --
	  	SD_CLK  : out std_logic
		;
		--Clocking (Page 5)
	  	CLK_IN  : in std_logic --Clock  (differential signal)
    );
end;

architecture only of SensorData is

--Constants----------------------------------------------------------------------------
----cg--entities/SensorData/constants--begin
  constant eHIL_ena : std_logic := '0'; --to enable (1) or disable (0) the eHIL test
  constant N        : integer   := 768;
  constant fixm_in  : integer   := 12;
  constant fixn_in  : integer   := 11;


----cg--entities/SensorData/constants--end

--Components---------------------------------------------------------------------------
----cg--entities/SensorData/components--begin
  COMPONENT PLL IS
  PORT
  (
	inclk0	: IN STD_LOGIC  := '0';
	c0		: OUT STD_LOGIC ;
	c1		: OUT STD_LOGIC 
  );
  END COMPONENT ;

  COMPONENT SOPC IS 
  port
  (
	clk :  IN  STD_LOGIC;
	reset_n :  IN  STD_LOGIC;
	sdram_dq :  INOUT  STD_LOGIC_VECTOR(31 downto 0);
	sdram_cas_n :  OUT  STD_LOGIC;
	sdram_cke :  OUT  STD_LOGIC;
	sdram_ras_n :  OUT  STD_LOGIC;
	sdram_we_n :  OUT  STD_LOGIC;
	sdram_cs_n :  OUT  STD_LOGIC;
	sdram_addr :  OUT  STD_LOGIC_VECTOR(12 downto 0);
	sdram_ba :  OUT  STD_LOGIC_VECTOR(1 downto 0);
	sdram_dqm :  OUT  STD_LOGIC_VECTOR(3 downto 0)
  );
  END COMPONENT ;

----cg--entities/SensorData/components--end

--Signals------------------------------------------------------------------------------
----cg--entities/SensorData/signals--begin

  --
  SIGNAL clk_50                      : STD_LOGIC;
  SIGNAL clk_50_sdram                : STD_LOGIC;                     
  SIGNAL reset_intern                : STD_LOGIC;
  SIGNAL reset_intern_n				 : STD_LOGIC;                       
  SIGNAL reset_count                 : STD_LOGIC_VECTOR(3 downto 0);


----cg--entities/SensorData/signals--end

begin
----cg--entities/SensorData/implement--begin


    -------------------
    --Reset Generator--
    -------------------
     ResetGen : process (clk_50)
     begin
       if clk_50='1' and clk_50'event then
         if reset_count /= "1111" then
           reset_count <= reset_count + 1;
           reset_intern    <= '1';
         else
           reset_intern    <= '0';
         end if;
       end if;
     end process;
    reset_intern_n <= not reset_intern;
  

    -------
    --PLL--
    -------
    PLL_Inst : PLL
    PORT MAP
    (
	  inclk0	=> CLK_IN,
	  c0		=> clk_50,
	  c1		=> clk_50_sdram
    );


    SD_CLK <= clk_50_sdram;   --Phaseshift from -30 to -60

   
    --------
    --NIOS--
    --------
    SOPC_Inst : SOPC 
    port map
    (
	  clk            => clk_50,
	  reset_n        => reset_intern_n,
	  sdram_dq       => SD_DQ,
	  sdram_cas_n    => SD_CAS_N,
	  sdram_cke      => SD_CKE,
	  sdram_ras_n    => SD_RAS_N,
	  sdram_we_n     => SD_WE_N,
	  sdram_cs_n     => SD_CS_N,
	  sdram_addr     => SD_A,
	  sdram_ba       => SD_BA,
	  sdram_dqm      => SD_DQM 
    );
	
	
    --------
    --ADCs--
    --------
	--ADCF_CLK <= clk_fs;
	--ADCM_CLK <= clk_fs;
	--ADCC_CLK <= clk_fs;



----cg--entities/SensorData/implement--end
end only;