sopc.vhd

nios sopc上的sram调试程序

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY SOPC IS 
	port
	(
		clk :  IN  STD_LOGIC;
		reset_n :  IN  STD_LOGIC;
		sdram_dq :  INOUT  STD_LOGIC_VECTOR(31 downto 0);
		sdram_cas_n :  OUT  STD_LOGIC;
		sdram_cke :  OUT  STD_LOGIC;
		sdram_ras_n :  OUT  STD_LOGIC;
		sdram_we_n :  OUT  STD_LOGIC;
		sdram_cs_n :  OUT  STD_LOGIC;
		sdram_addr :  OUT  STD_LOGIC_VECTOR(12 downto 0);
		sdram_ba :  OUT  STD_LOGIC_VECTOR(1 downto 0);
		sdram_dqm :  OUT  STD_LOGIC_VECTOR(3 downto 0)
	);
END SOPC;

ARCHITECTURE bdf_type OF SOPC IS 

component nios
	PORT(clk : IN STD_LOGIC;
		 reset_n : IN STD_LOGIC;
		 zs_dq_to_and_from_the_sdram : INOUT STD_LOGIC_VECTOR(31 downto 0);
		 zs_cas_n_from_the_sdram : OUT STD_LOGIC;
		 zs_cke_from_the_sdram : OUT STD_LOGIC;
		 zs_cs_n_from_the_sdram : OUT STD_LOGIC;
		 zs_ras_n_from_the_sdram : OUT STD_LOGIC;
		 zs_we_n_from_the_sdram : OUT STD_LOGIC;
		 zs_addr_from_the_sdram : OUT STD_LOGIC_VECTOR(12 downto 0);
		 zs_ba_from_the_sdram : OUT STD_LOGIC_VECTOR(1 downto 0);
		 zs_dqm_from_the_sdram : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;



BEGIN 



b2v_inst : nios
PORT MAP(clk => clk,
		 reset_n => reset_n,
		 zs_dq_to_and_from_the_sdram => sdram_dq,
		 zs_cas_n_from_the_sdram => sdram_cas_n,
		 zs_cke_from_the_sdram => sdram_cke,
		 zs_cs_n_from_the_sdram => sdram_cs_n,
		 zs_ras_n_from_the_sdram => sdram_ras_n,
		 zs_we_n_from_the_sdram => sdram_we_n,
		 zs_addr_from_the_sdram => sdram_addr,
		 zs_ba_from_the_sdram => sdram_ba,
		 zs_dqm_from_the_sdram => sdram_dqm);

END;