startcode.s

IARSOURCECODE是基于LPC2478嵌入式软件IAR EWARM V4.42的应用实例代码

;//     <o7.16..17>  PCLK_UART2: Peripheral Clock Selection for UART2
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//     <o7.18..19>  PCLK_UART3: Peripheral Clock Selection for UART3
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//     <o7.20..21>   PCLK_I2C2: Peripheral Clock Selection for I2C2
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//     <o7.22..23>    PCLK_I2S: Peripheral Clock Selection for I2S
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//     <o7.24..25>    PCLK_MCI: Peripheral Clock Selection for MCI
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//     <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Cclk / 8
;//   </h>
;// </e>
CLOCK_SETUP     DEFINE     1
SCS_Val         DEFINE     0x00000020
CLKSRCSEL_Val   DEFINE     0x00000001
PLLCFG_Val      DEFINE     0x0000000B
CCLKCFG_Val     DEFINE     0x00000004
USBCLKCFG_Val   DEFINE     0x00000005
PCLKSEL0_Val    DEFINE     0x00000000
PCLKSEL1_Val    DEFINE     0x00000000


; Memory Accelerator Module (MAM) definitions
MAM_BASE        DEFINE     0xE01FC000      ; MAM Base Address
MAMCR_OFS       DEFINE     0x00            ; MAM Control Offset
MAMTIM_OFS      DEFINE     0x04            ; MAM Timing Offset

;// <e> MAM Setup
;//   <o1.0..1>   MAM Control
;//               <0=> Disabled
;//               <1=> Partially Enabled
;//               <2=> Fully Enabled
;//               <i> Mode
;//   <o2.0..2>   MAM Timing
;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
;//               <i> Fetch Cycles
;// </e>
MAM_SETUP       DEFINE     1
MAMCR_Val       DEFINE     0x00000002
MAMTIM_Val      DEFINE     0x00000004

; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.

        PROGRAM	?RESET
        COMMON	INTVEC:CODE(3)
        PUBLIC  __program_start
        EXTERN	Reset_Handler, Undef_Handler, SWI_Handler, PAbt_Handler, DAbt_Handler, FIQ_Handler
        CODE32	; Always ARM mode after reset

__program_start
        LDR     PC, =Reset_Handler
        LDR     PC, =Undef_Handler
        LDR     PC, =SWI_Handler
        LDR     PC, =PAbt_Handler
        LDR     PC, =DAbt_Handler
        B       .
        LDR     PC, [PC, #-0x0120]  ; Vector from VicVectAddr
        LDR     PC, =FIQ_Handler

        LTORG
        ENDMOD

; Reset Handler

        MODULE	?CSTARTUP
        RSEG	IRQ_STACK:DATA(3)
        RSEG	FIQ_STACK:DATA(3)
        RSEG	SVC_STACK:DATA(3)
        RSEG	ABT_STACK:DATA(3)
        RSEG	UND_STACK:DATA(3)
        RSEG	CSTACK:DATA(3)
        RSEG	ICODE:CODE(3)
        PUBLIC	Reset_Handler, Undef_Handler, SWI_Handler, PAbt_Handler, DAbt_Handler, FIQ_Handler
        EXTERN	?main
        CODE32

Reset_Handler

; Setup Clock
                IF      CLOCK_SETUP != 0
                LDR     R0, =SCB_BASE
                MOV     R1, #0xAA
                MOV     R2, #0x55
;  Configure and Enable PLL
                LDR     R3, =SCS_Val          ; Enable main oscillator
                STR     R3, [R0, #SCS_OFS] 

                IF      (SCS_Val&OSCEN) != 0  
OSC_Loop        LDR     R3, [R0, #SCS_OFS]    ; Wait for main osc stabilize
                ANDS    R3, R3, #OSCSTAT
                BEQ     OSC_Loop
                ENDIF

                LDR     R3, =CLKSRCSEL_Val    ; Select PLL source clock
                STR     R3, [R0, #CLKSRCSEL_OFS] 
                LDR     R3, =PLLCFG_Val
                STR     R3, [R0, #PLLCFG_OFS] 
                STR     R1, [R0, #PLLFEED_OFS]
                STR     R2, [R0, #PLLFEED_OFS]
                MOV     R3, #PLLCON_PLLE
                STR     R3, [R0, #PLLCON_OFS]
                STR     R1, [R0, #PLLFEED_OFS]
                STR     R2, [R0, #PLLFEED_OFS]

;  Wait until PLL Locked
PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
                ANDS    R3, R3, #PLLSTAT_PLOCK
                BEQ     PLL_Loop

M_N_Lock        LDR     R3, [R0, #PLLSTAT_OFS]
                LDR     R4, =(PLLSTAT_M|PLLSTAT_N)
                AND     R3, R3, R4
                LDR     R4, =PLLCFG_Val
                EORS    R3, R3, R4
                BNE     M_N_Lock

;  Setup CPU clock divider
                MOV     R3, #CCLKCFG_Val
                STR     R3, [R0, #CCLKCFG_OFS]

;  Setup USB clock divider
                LDR     R3, =USBCLKCFG_Val
                STR     R3, [R0, #USBCLKCFG_OFS]

;  Setup Peripheral Clock
                LDR     R3, =PCLKSEL0_Val
                STR     R3, [R0, #PCLKSEL0_OFS]
                LDR     R3, =PCLKSEL1_Val
                STR     R3, [R0, #PCLKSEL1_OFS]

;  Switch to PLL Clock
                MOV     R3, #(PLLCON_PLLE|PLLCON_PLLC)
                STR     R3, [R0, #PLLCON_OFS]
                STR     R1, [R0, #PLLFEED_OFS]
                STR     R2, [R0, #PLLFEED_OFS]
                ENDIF   ; CLOCK_SETUP


; Setup MAM
                IF      MAM_SETUP != 0
                LDR     R0, =MAM_BASE
                MOV     R1, #MAMTIM_Val
                STR     R1, [R0, #MAMTIM_OFS] 
                MOV     R1, #MAMCR_Val
                STR     R1, [R0, #MAMCR_OFS] 
                ENDIF   ; MAM_SETUP


; Memory Mapping (when Interrupt Vectors are in RAM) 
                
;  Enter Undefined Instruction Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit
        LDR	    SP, =SFE(UND_STACK)&0xFFFFFFF8

;  Enter Abort Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit
        LDR	    SP, =SFE(ABT_STACK)&0xFFFFFFF8

;  Enter FIQ Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit
        LDR	    SP, =SFE(FIQ_STACK)&0xFFFFFFF8

;  Enter IRQ Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit
        LDR	    SP, =SFE(IRQ_STACK)&0xFFFFFFF8

;  Enter Supervisor Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
        LDR	    SP, =SFE(SVC_STACK)&0xFFFFFFF8

;  Enter User Mode and set its Stack Pointer
        MSR     CPSR_c, #Mode_USR
        LDR	    SP, =SFE(CSTACK)&0xFFFFFFF8

; Enter the C code

        LDR     R0, =?main
        BX      R0
        B       .

Undef_Handler
SWI_Handler
PAbt_Handler
DAbt_Handler
FIQ_Handler
        B       .

        LTORG
        ENDMOD
        END