📄 os_cpu_a.lst
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rn from this except
ARM Macro Assembler Page 10
ion: -4.
357 00000120 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
358 00000124 E1A0300E MOV R3, LR ; Save link registe
r.
359 00000128 E3A00003 MOV R0, #OS_CPU_ARM_EXCEPT_PREFETCH
_ABORT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_PREFETCH_ABORT.
360 0000012C EA000013 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
361 00000130
362 00000130
363 00000130 ;*******************************************************
*************************************************
364 00000130 ; DATA ABORT EXCEPTI
ON HANDLER
365 00000130 ;
366 00000130 ; Register Usage: R0 Exception Type
367 00000130 ; R1
368 00000130 ; R2
369 00000130 ; R3 Return PC
370 00000130 ;*******************************************************
*************************************************
371 00000130
372 00000130 AREA CODE, CODE, READONLY
373 00000130 CODE32
374 00000130
375 00000130 OS_CPU_ARM_ExceptDataAbortHndlr
376 00000130 E24EE008 SUB LR, LR, #8 ; LR offset to retu
rn from this except
ion: -8.
377 00000134 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
378 00000138 E1A0300E MOV R3, LR ; Save link registe
r.
379 0000013C E3A00004 MOV R0, #OS_CPU_ARM_EXCEPT_DATA_ABO
RT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_DATA_ABORT.
380 00000140 EA00000E B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
381 00000144
382 00000144
383 00000144 ;*******************************************************
*************************************************
384 00000144 ; ADDRESS ABORT EXCEP
TION HANDLER
385 00000144 ;
386 00000144 ; Register Usage: R0 Exception Type
387 00000144 ; R1
388 00000144 ; R2
389 00000144 ; R3 Return PC
390 00000144 ;*******************************************************
*************************************************
ARM Macro Assembler Page 11
391 00000144
392 00000144 AREA CODE, CODE, READONLY
393 00000144 CODE32
394 00000144
395 00000144 OS_CPU_ARM_ExceptAddrAbortHndlr
396 00000144 E24EE008 SUB LR, LR, #8 ; LR offset to retu
rn from this except
ion: -8.
397 00000148 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
398 0000014C E1A0300E MOV R3, LR ; Save link registe
r.
399 00000150 E3A00005 MOV R0, #OS_CPU_ARM_EXCEPT_ADDR_ABO
RT
; Set exception ID
to OS_CPU_ARM_EXCEP
T_ADDR_ABORT.
400 00000154 EA000009 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
401 00000158
402 00000158
403 00000158 ;*******************************************************
*************************************************
404 00000158 ; INTERRUPT REQUEST EXC
EPTION HANDLER
405 00000158 ;
406 00000158 ; Register Usage: R0 Exception Type
407 00000158 ; R1
408 00000158 ; R2
409 00000158 ; R3 Return PC
410 00000158 ;*******************************************************
*************************************************
411 00000158
412 00000158 AREA CODE, CODE, READONLY
413 00000158 CODE32
414 00000158
415 00000158 OS_CPU_ARM_ExceptIrqHndlr
416 00000158 E24EE004 SUB LR, LR, #4 ; LR offset to retu
rn from this except
ion: -4.
417 0000015C E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
418 00000160 E1A0300E MOV R3, LR ; Save link registe
r.
419 00000164 E3A00006 MOV R0, #OS_CPU_ARM_EXCEPT_IRQ ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_IR
Q.
420 00000168 EA000004 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
421 0000016C
422 0000016C
423 0000016C ;*******************************************************
*************************************************
424 0000016C ; FAST INTERRUPT REQUEST E
XCEPTION HANDLER
425 0000016C ;
ARM Macro Assembler Page 12
426 0000016C ; Register Usage: R0 Exception Type
427 0000016C ; R1
428 0000016C ; R2
429 0000016C ; R3 Return PC
430 0000016C ;*******************************************************
*************************************************
431 0000016C
432 0000016C AREA CODE, CODE, READONLY
433 0000016C CODE32
434 0000016C
435 0000016C OS_CPU_ARM_ExceptFiqHndlr
436 0000016C E24EE004 SUB LR, LR, #4 ; LR offset to retu
rn from this except
ion: -4.
437 00000170 E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
438 00000174 E1A0300E MOV R3, LR ; Save link registe
r.
439 00000178 E3A00007 MOV R0, #OS_CPU_ARM_EXCEPT_FIQ ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_FI
Q.
440 0000017C EAFFFFFF B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
441 00000180
442 00000180
443 00000180 ;*******************************************************
*************************************************
444 00000180 ; GLOBAL EXCEPTION
HANDLER
445 00000180 ;
446 00000180 ; Register Usage: R0 Exception Type
447 00000180 ; R1 Exception's SPSR
448 00000180 ; R2 Old CPU mode
449 00000180 ; R3 Return PC
450 00000180 ;*******************************************************
*************************************************
451 00000180
452 00000180 AREA CODE, CODE, READONLY
453 00000180 CODE32
454 00000180
455 00000180 OS_CPU_ARM_ExceptHndlr
456 00000180 E14F1000 MRS R1, SPSR ; Save CPSR (i.e. e
xception's SPSR).
457 00000184
458 00000184 ; DETERMINE IF WE INTERRUPTED A TASK OR ANOTHER LOWER PR
IORITY EXCEPTION:
459 00000184 ; SPSR.Mode = SVC : task,
460 00000184 ; SPSR.Mode = FIQ, IRQ, ABT, UND : other exceptions,
461 00000184 ; SPSR.Mode = USR : *unsupported state*
.
462 00000184 E201201F AND R2, R1, #OS_CPU_ARM_MODE_MASK
463 00000188 E3520013 CMP R2, #OS_CPU_ARM_MODE_SVC
464 0000018C 1A00001F BNE OS_CPU_ARM_ExceptHndlr_BreakExc
ept
465 00000190
466 00000190
467 00000190 ;*******************************************************
ARM Macro Assembler Page 13
*************************************************
468 00000190 ; EXCEPTION HANDLER: TA
SK INTERRUPTED
469 00000190 ;
470 00000190 ; Register Usage: R0 Exception Type
471 00000190 ; R1 Exception's SPSR
472 00000190 ; R2 Exception's CPSR
473 00000190 ; R3 Return PC
474 00000190 ; R4 Exception's SP
475 00000190 ;*******************************************************
*************************************************
476 00000190
477 00000190 AREA CODE, CODE, READONLY
478 00000190 CODE32
479 00000190
480 00000190 OS_CPU_ARM_ExceptHndlr_BreakTask
481 00000190 E10F2000 MRS R2, CPSR ; Save exception's
CPSR.
482 00000194 E1A0400D MOV R4, SP ; Save exception's
stack pointer.
483 00000198
484 00000198 ; Change to SVC mode & disable interruptions.
485 00000198 E321F0D3 MSR CPSR_c, #(OS_CPU_ARM_CONTROL_IN
T_DIS | OS_CPU_ARM_MODE_SVC)
486 0000019C
487 0000019C ; SAVE TASK'S CONTEXT ONTO TASK'S STACK:
488 0000019C E92D0008 STMFD SP!, {R3} ; Push task's PC,
489 000001A0 E92D4000 STMFD SP!, {LR} ; Push task's LR,
490 000001A4 E92D1FE0 STMFD SP!, {R5-R12} ; Push task's R
12-R5,
491 000001A8 E8B403E0 LDMFD R4!, {R5-R9} ; Move task's R4
-R0 from exception
stack to task's sta
ck.
492 000001AC E92D03E0 STMFD SP!, {R5-R9}
493 000001B0 E92D0002 STMFD SP!, {R1} ; Push task's CPS
R (i.e. exception S
PSR).
494 000001B4
495 000001B4 ; if (OSRunning == 1)
496 000001B4 E59F1098 LDR R1, __OS_Running
497 000001B8 E5D11000 LDRB R1, [R1]
498 000001BC E3510001 CMP R1, #1
499 000001C0 1A000006 BNE OS_CPU_ARM_ExceptHndlr_BreakTas
k_1
500 000001C4
501 000001C4 ; HANDLE NESTING COUNTER:
502 000001C4 E59F309C LDR R3, __OS_IntNesting
; OSIntNesting++;
503 000001C8 E5D34000 LDRB R4, [R3]
504 000001CC E2844001 ADD R4, R4, #1
505 000001D0 E5C34000 STRB R4, [R3]
506 000001D4
507 000001D4 E59F3084 LDR R3, __OS_TCBCur ; OSTCBCur->O
STCBStkPtr = SP;
508 000001D8 E5934000 LDR R4, [R3]
ARM Macro Assembler Page 14
509 000001DC E584D000 STR SP, [R4]
510 000001E0
511 000001E0 OS_CPU_ARM_ExceptHndlr_BreakTask_1
512 000001E0 E12FF002 MSR CPSR_cxsf, R2 ; RESTORE INTERRU
PTED MODE.
513 000001E4
514 000001E4 ; EXECUTE EXCEPTION HANDLER:
515 000001E4 E59F1088 LDR R1, __OS_CPU_ExceptHndlr ; OS_C
PU_ExceptHndlr(exce
pt_type = R0);
516 000001E8 E1A0E00F MOV LR, PC
517 000001EC E12FFF11 BX R1
518 000001F0
519 000001F0 ; Adjust exception stack pointer. This is needed becaus
e
520 000001F0 ; exception stack is not used when restoring task contex
t.
521 000001F0 E28DD038 ADD SP, SP, #(14 * 4)
522 000001F4
523 000001F4 ; Change to SVC mode & disable interruptions.
524 000001F4 E321F0D3 MSR CPSR_c, #(OS_CPU_ARM_CONTROL_IN
T_DIS | OS_CPU_ARM_MODE_SVC)
525 000001F8
526 000001F8 ; Call OSIntExit(). This call MAY never return if a rea
dy
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