📄 os_cpu_a.lst
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ter,
169 0000003C E590D000 LDR SP, [R0] ; Switch to the
new stack,
170 00000040
171 00000040 E49D0004 LDR R0, [SP], #4 ; Pop new task'
s CPSR,
172 00000044 E16FF000 MSR SPSR_cxsf, R0
173 00000048
174 00000048 E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
175 0000004C
176 0000004C
177 0000004C ;*******************************************************
**************************************************
178 0000004C ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
179 0000004C ;
180 0000004C ; Note(s) : 1) OSCtxSw() is called in SVC mode with BOTH
FIQ and IRQ interrupts DISABLED.
181 0000004C ;
182 0000004C ; 2) The pseudo-code for OSCtxSw() is:
183 0000004C ; a) Save the current task's context onto t
he current task's stack,
184 0000004C ; b) OSTCBCur->OSTCBStkPtr = SP;
185 0000004C ; c) OSTaskSwHook();
186 0000004C ; d) OSPrioCur = OSPrioHighRdy;
187 0000004C ; e) OSTCBCur = OSTCBHighRdy;
188 0000004C ; f) SP = OSTCBHighRdy->
OSTCBStkPtr;
189 0000004C ; g) Restore the new task's context from th
e new task's stack,
ARM Macro Assembler Page 6
190 0000004C ; h) Return to new task's code.
191 0000004C ;
192 0000004C ; 3) Upon entry:
193 0000004C ; OSTCBCur points to the OS_TCB of the
task to suspend,
194 0000004C ; OSTCBHighRdy points to the OS_TCB of the
task to resume.
195 0000004C ;*******************************************************
**************************************************
196 0000004C
197 0000004C AREA CODE, CODE, READONLY
198 0000004C CODE32
199 0000004C
200 0000004C OSCtxSw
201 0000004C ; SAVE CURRENT TASK'S CONTEXT:
202 0000004C E92D4000 STMFD SP!, {LR} ; Push return a
ddress,
203 00000050 E92D4000 STMFD SP!, {LR}
204 00000054 E92D1FFF STMFD SP!, {R0-R12} ; Push regist
ers,
205 00000058 E10F0000 MRS R0, CPSR ; Push current
CPSR,
206 0000005C E31E0001 TST LR, #1 ; See if called
from Thumb mode,
207 00000060 13800020 ORRNE R0, R0, #OS_CPU_ARM_CONTROL_THU
MB
; If yes, set t
he T-bit.
208 00000064 E92D0001 STMFD SP!, {R0}
209 00000068
210 00000068 E59F01F0 LDR R0, __OS_TCBCur ; OSTCBCur->OST
CBStkPtr = SP;
211 0000006C E5901000 LDR R1, [R0]
212 00000070 E581D000 STR SP, [R1]
213 00000074
214 00000074 E59F01F0 LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
215 00000078 E1A0E00F MOV LR, PC
216 0000007C E12FFF10 BX R0
217 00000080
218 00000080 E59F01D0 LDR R0, __OS_PrioCur ; OSPrioCur =
OSPrioHighRdy;
219 00000084 E59F11D0 LDR R1, __OS_PrioHighRdy
220 00000088 E5D12000 LDRB R2, [R1]
221 0000008C E5C02000 STRB R2, [R0]
222 00000090
223 00000090 E59F01C8 LDR R0, __OS_TCBCur ; OSTCBCur = O
STCBHighRdy;
224 00000094 E59F11C8 LDR R1, __OS_TCBHighRdy
225 00000098 E5912000 LDR R2, [R1]
226 0000009C E5802000 STR R2, [R0]
227 000000A0
228 000000A0 E592D000 LDR SP, [R2] ; SP = OSTCBHighRdy
->OSTCBStkPtr;
229 000000A4
230 000000A4 ; RESTORE NEW TASK'S CONTEXT:
231 000000A4 E8BD0001 LDMFD SP!, {R0} ; Pop new task's
CPSR,
232 000000A8 E16FF000 MSR SPSR_cxsf, R0
ARM Macro Assembler Page 7
233 000000AC
234 000000AC E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
235 000000B0
236 000000B0
237 000000B0 ;*******************************************************
**************************************************
238 000000B0 ; PERFORM A CONTEXT SWITCH (From int
errupt level) - OSIntCtxSw()
239 000000B0 ;
240 000000B0 ; Note(s) : 1) OSIntCtxSw() is called in SVC mode with B
OTH FIQ and IRQ interrupts DISABLED.
241 000000B0 ;
242 000000B0 ; 2) The pseudo-code for OSCtxSw() is:
243 000000B0 ; a) OSTaskSwHook();
244 000000B0 ; b) OSPrioCur = OSPrioHighRdy;
245 000000B0 ; c) OSTCBCur = OSTCBHighRdy;
246 000000B0 ; d) SP = OSTCBHighRdy->
OSTCBStkPtr;
247 000000B0 ; e) Restore the new task's context from th
e new task's stack,
248 000000B0 ; f) Return to new task's code.
249 000000B0 ;
250 000000B0 ; 3) Upon entry:
251 000000B0 ; OSTCBCur points to the OS_TCB of the
task to suspend,
252 000000B0 ; OSTCBHighRdy points to the OS_TCB of the
task to resume.
253 000000B0 ;*******************************************************
**************************************************
254 000000B0
255 000000B0 AREA CODE, CODE, READONLY
256 000000B0 CODE32
257 000000B0
258 000000B0 OSIntCtxSw
259 000000B0 E59F01B4 LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
260 000000B4 E1A0E00F MOV LR, PC
261 000000B8 E12FFF10 BX R0
262 000000BC
263 000000BC E59F0194 LDR R0, __OS_PrioCur ; OSPrioCur =
OSPrioHighRdy;
264 000000C0 E59F1194 LDR R1, __OS_PrioHighRdy
265 000000C4 E5D12000 LDRB R2, [R1]
266 000000C8 E5C02000 STRB R2, [R0]
267 000000CC
268 000000CC E59F018C LDR R0, __OS_TCBCur ; OSTCBCur = O
STCBHighRdy;
269 000000D0 E59F118C LDR R1, __OS_TCBHighRdy
270 000000D4 E5912000 LDR R2, [R1]
271 000000D8 E5802000 STR R2, [R0]
272 000000DC
273 000000DC E592D000 LDR SP, [R2] ; SP = OSTCBHighRdy
->OSTCBStkPtr;
274 000000E0
275 000000E0 ; RESTORE NEW TASK'S CONTEXT:
276 000000E0 E8BD0001 LDMFD SP!, {R0} ; Pop new task's
ARM Macro Assembler Page 8
CPSR,
277 000000E4 E16FF000 MSR SPSR_cxsf, R0
278 000000E8
279 000000E8 E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^ ; Pop
new task's context
.
280 000000EC
281 000000EC
282 000000EC ;*******************************************************
*************************************************
283 000000EC ; RESET EXCEPTION
HANDLER
284 000000EC ;
285 000000EC ; Register Usage: R0 Exception Type
286 000000EC ; R1
287 000000EC ; R2
288 000000EC ; R3 Return PC
289 000000EC ;*******************************************************
*************************************************
290 000000EC
291 000000EC AREA CODE, CODE, READONLY
292 000000EC CODE32
293 000000EC
294 000000EC OS_CPU_ARM_ExceptResetHndlr
295 000000EC ; LR offset to return from this exception: 0.
296 000000EC ; (there is no way to return from a RESET exception).
297 000000EC E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
298 000000F0 E1A0300E MOV R3, LR ; Save link registe
r.
299 000000F4 E3A00000 MOV R0, #OS_CPU_ARM_EXCEPT_RESET ;
Set exception ID to
OS_CPU_ARM_EXCEPT_
RESET.
300 000000F8 EA000020 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
301 000000FC
302 000000FC
303 000000FC ;*******************************************************
*************************************************
304 000000FC ; UNDEFINED INSTRUCTION E
XCEPTION HANDLER
305 000000FC ;
306 000000FC ; Register Usage: R0 Exception Type
307 000000FC ; R1
308 000000FC ; R2
309 000000FC ; R3 Return PC
310 000000FC ;*******************************************************
*************************************************
311 000000FC
312 000000FC AREA CODE, CODE, READONLY
313 000000FC CODE32
314 000000FC
315 000000FC OS_CPU_ARM_ExceptUndefInstrHndlr
316 000000FC ; LR offset to return from this exception: 0.
317 000000FC E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
318 00000100 E1A0300E MOV R3, LR ; Save link registe
ARM Macro Assembler Page 9
r.
319 00000104 E3A00001 MOV R0, #OS_CPU_ARM_EXCEPT_UNDEF_IN
STR
; Set exception ID
to OS_CPU_ARM_EXCEP
T_UNDEF_INSTR.
320 00000108 EA00001C B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
321 0000010C
322 0000010C
323 0000010C ;*******************************************************
*************************************************
324 0000010C ; SOFTWARE INTERRUPT EXC
EPTION HANDLER
325 0000010C ;
326 0000010C ; Register Usage: R0 Exception Type
327 0000010C ; R1
328 0000010C ; R2
329 0000010C ; R3 Return PC
330 0000010C ;*******************************************************
*************************************************
331 0000010C
332 0000010C AREA CODE, CODE, READONLY
333 0000010C CODE32
334 0000010C
335 0000010C OS_CPU_ARM_ExceptSwiHndlr
336 0000010C ; LR offset to return from this exception: 0.
337 0000010C E92D5FFF STMFD SP!, {R0-R12, LR} ; Push workin
g registers.
338 00000110 E1A0300E MOV R3, LR ; Save link registe
r.
339 00000114 E3A00002 MOV R0, #OS_CPU_ARM_EXCEPT_SWI ; Se
t exception ID to O
S_CPU_ARM_EXCEPT_SW
I.
340 00000118 EA000018 B OS_CPU_ARM_ExceptHndlr ; Branch
to global exceptio
n handler.
341 0000011C
342 0000011C
343 0000011C ;*******************************************************
*************************************************
344 0000011C ; PREFETCH ABORT EXCEP
TION HANDLER
345 0000011C ;
346 0000011C ; Register Usage: R0 Exception Type
347 0000011C ; R1
348 0000011C ; R2
349 0000011C ; R3 Return PC
350 0000011C ;*******************************************************
*************************************************
351 0000011C
352 0000011C AREA CODE, CODE, READONLY
353 0000011C CODE32
354 0000011C
355 0000011C OS_CPU_ARM_ExceptPrefetchAbortHndlr
356 0000011C E24EE004 SUB LR, LR, #4 ; LR offset to retu
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