📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;
2 00000000 ;*******************************************************
*************************************************
3 00000000 ; uC/OS-II
4 00000000 ; The Real-Time
Kernel
5 00000000 ;
6 00000000 ;
7 00000000 ; (c) Copyright 1992-2007, M
icrium, Weston, FL
8 00000000 ; All Rights Re
served
9 00000000 ;
10 00000000 ; Generic ARM
Port
11 00000000 ;
12 00000000 ; File : OS_CPU_A.ASM
13 00000000 ; Version : V1.82
14 00000000 ; By : Jean J. Labrosse
15 00000000 ; Jean-Denis Hatier
16 00000000 ;
17 00000000 ; For : ARM7 or ARM9
18 00000000 ; Mode : ARM or Thumb
19 00000000 ; Toolchain : Keil uVision with the ARM RealView Compile
r (RVMDK)
20 00000000 ;*******************************************************
*************************************************
21 00000000 ;
22 00000000
23 00000000 ;*******************************************************
*************************************************
24 00000000 ; PUBLIC FUNCT
IONS
25 00000000 ;*******************************************************
*************************************************
26 00000000 ; External references.
27 00000000 IMPORT OSRunning
28 00000000 IMPORT OSPrioCur
29 00000000 IMPORT OSPrioHighRdy
30 00000000 IMPORT OSTCBCur
31 00000000 IMPORT OSTCBHighRdy
32 00000000 IMPORT OSIntNesting
33 00000000 IMPORT OSIntExit
34 00000000 IMPORT OSTaskSwHook
35 00000000
36 00000000 ; Functions declared in this file.
37 00000000 EXPORT OS_CPU_SR_Save
38 00000000 EXPORT OS_CPU_SR_Restore
39 00000000 EXPORT OSStartHighRdy
40 00000000 EXPORT OSCtxSw
41 00000000 EXPORT OSIntCtxSw
42 00000000
43 00000000 ; Functions related to exception handling.
44 00000000 EXPORT OS_CPU_ARM_ExceptResetHndlr
45 00000000 EXPORT OS_CPU_ARM_ExceptUndefInstrHndl
r
46 00000000 EXPORT OS_CPU_ARM_ExceptSwiHndlr
47 00000000 EXPORT OS_CPU_ARM_ExceptPrefetchAbortH
ARM Macro Assembler Page 2
ndlr
48 00000000 EXPORT OS_CPU_ARM_ExceptDataAbortHndlr
49 00000000 EXPORT OS_CPU_ARM_ExceptAddrAbortHndlr
50 00000000 EXPORT OS_CPU_ARM_ExceptIrqHndlr
51 00000000 EXPORT OS_CPU_ARM_ExceptFiqHndlr
52 00000000
53 00000000 IMPORT OS_CPU_ExceptHndlr
54 00000000
55 00000000
56 00000000 ;*******************************************************
*************************************************
57 00000000 ; EQUATES
58 00000000 ;*******************************************************
*************************************************
59 00000000
60 00000000 000000C0
OS_CPU_ARM_CONTROL_INT_DIS
EQU 0xC0 ; Disable both FIQ
and IRQ.
61 00000000 00000040
OS_CPU_ARM_CONTROL_FIQ_DIS
EQU 0x40 ; Disable FIQ.
62 00000000 00000080
OS_CPU_ARM_CONTROL_IRQ_DIS
EQU 0x80 ; Disable IRQ.
63 00000000 00000020
OS_CPU_ARM_CONTROL_THUMB
EQU 0x20 ; Set THUMB mode.
64 00000000 00000000
OS_CPU_ARM_CONTROL_ARM
EQU 0x00 ; Set ARM mode.
65 00000000
66 00000000 0000001F
OS_CPU_ARM_MODE_MASK
EQU 0x1F
67 00000000 00000010
OS_CPU_ARM_MODE_USR
EQU 0x10
68 00000000 00000011
OS_CPU_ARM_MODE_FIQ
EQU 0x11
69 00000000 00000012
OS_CPU_ARM_MODE_IRQ
EQU 0x12
70 00000000 00000013
OS_CPU_ARM_MODE_SVC
EQU 0x13
71 00000000 00000017
OS_CPU_ARM_MODE_ABT
EQU 0x17
72 00000000 0000001B
OS_CPU_ARM_MODE_UND
EQU 0x1B
73 00000000 0000001F
OS_CPU_ARM_MODE_SYS
EQU 0x1F
74 00000000
75 00000000 00000000
ARM Macro Assembler Page 3
OS_CPU_ARM_EXCEPT_RESET
EQU 0x00
76 00000000 00000001
OS_CPU_ARM_EXCEPT_UNDEF_INSTR
EQU 0x01
77 00000000 00000002
OS_CPU_ARM_EXCEPT_SWI
EQU 0x02
78 00000000 00000003
OS_CPU_ARM_EXCEPT_PREFETCH_ABORT
EQU 0x03
79 00000000 00000004
OS_CPU_ARM_EXCEPT_DATA_ABORT
EQU 0x04
80 00000000 00000005
OS_CPU_ARM_EXCEPT_ADDR_ABORT
EQU 0x05
81 00000000 00000006
OS_CPU_ARM_EXCEPT_IRQ
EQU 0x06
82 00000000 00000007
OS_CPU_ARM_EXCEPT_FIQ
EQU 0x07
83 00000000
84 00000000
85 00000000 ;*******************************************************
*************************************************
86 00000000 ; CODE GENERATION D
IRECTIVES
87 00000000 ;*******************************************************
*************************************************
88 00000000
89 00000000 REQUIRE8
90 00000000 PRESERVE8
91 00000000
92 00000000 ;*******************************************************
**************************************************
93 00000000 ; CRITICAL SECTION METH
OD 3 FUNCTIONS
94 00000000 ;
95 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
96 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
97 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
98 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
99 00000000 ; into the CPU's status register.
100 00000000 ;
101 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save (void);
102 00000000 ; void OS_CPU_SR_Restore (OS_CPU_SR
os_cpu_sr);
103 00000000 ;
104 00000000 ;
105 00000000 ; Note(s) : (1) These functions are used in general l
ike this:
106 00000000 ;
107 00000000 ; void Task (void *p_arg)
ARM Macro Assembler Page 4
108 00000000 ; {
109 00000000 ;
/* Allocate storage for CPU status register.
*/
110 00000000 ; #if (OS_CRITICAL_METHOD == 3)
111 00000000 ; OS_CPU_SR os_cpu_sr;
112 00000000 ; #endif
113 00000000 ;
114 00000000 ; :
115 00000000 ; :
116 00000000 ; OS_ENTER_CRITICAL();
/* os_cpu_sr = OS_CPU_SR_Save();
*/
117 00000000 ; :
118 00000000 ; :
119 00000000 ; OS_EXIT_CRITICAL();
/* OS_CPU_SR_Restore(cpu_sr);
*/
120 00000000 ; :
121 00000000 ; :
122 00000000 ; }
123 00000000 ;*******************************************************
**************************************************
124 00000000
125 00000000 AREA CODE, CODE, READONLY
126 00000000 CODE32
127 00000000
128 00000000 OS_CPU_SR_Save
129 00000000 E10F0000 MRS R0, CPSR
130 00000004 E38010C0 ORR R1, R0, #OS_CPU_ARM_CONTROL_INT
_DIS
; Set IRQ and FIQ b
its in CPSR to disa
ble all interrupts.
131 00000008 E121F001 MSR CPSR_c, R1
132 0000000C E12FFF1E BX LR ; Disabled, return
the original CPSR c
ontents in R0.
133 00000010
134 00000010
135 00000010 OS_CPU_SR_Restore
136 00000010 E121F000 MSR CPSR_c, R0
137 00000014 E12FFF1E BX LR
138 00000018
139 00000018
140 00000018 ;*******************************************************
**************************************************
141 00000018 ; START MULTIT
ASKING
142 00000018 ; void OSStartHigh
Rdy(void)
143 00000018 ;
144 00000018 ; Note(s) : 1) OSStartHighRdy() MUST:
145 00000018 ; a) Call OSTaskSwHook() then,
146 00000018 ; b) Set OSRunning to TRUE,
147 00000018 ; c) Switch to the highest priority task.
148 00000018 ;*******************************************************
**************************************************
ARM Macro Assembler Page 5
149 00000018
150 00000018 AREA CODE, CODE, READONLY
151 00000018 CODE32
152 00000018
153 00000018 OSStartHighRdy
154 00000018
155 00000018 ; Change to SVC mode.
156 00000018 E321F0D3 MSR CPSR_c, #(OS_CPU_ARM_CONTROL_IN
T_DIS | OS_CPU_ARM_MODE_SVC)
157 0000001C
158 0000001C E59F0248 LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
159 00000020 E1A0E00F MOV LR, PC
160 00000024 E12FFF10 BX R0
161 00000028
162 00000028 E59F0224 LDR R0, __OS_Running
; OSRunning = TRUE;
163 0000002C E3A01001 MOV R1, #1
164 00000030 E5C01000 STRB R1, [R0]
165 00000034
166 00000034 ; SWITCH TO HIGHEST PRIORITY TASK:
167 00000034 E59F0228 LDR R0, __OS_TCBHighRdy ; Get hi
ghest priority task
TCB address,
168 00000038 E5900000 LDR R0, [R0] ; Get stack poin
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