📄 cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/CPU
3 00000000 ; CPU CONFIGURATION &
PORT LAYER
4 00000000 ;
5 00000000 ; (c) Copyright 2004-2007; Micr
ium, Inc.; Weston, FL
6 00000000 ;
7 00000000 ; All rights reserved. Protected by inter
national copyright laws.
8 00000000 ;
9 00000000 ; uC/CPU is provided in source form for FR
EE evaluation, for educational
10 00000000 ; use or peaceful research. If you plan o
n using uC/CPU in a commercial
11 00000000 ; product you need to contact Micrium to p
roperly license its use in your
12 00000000 ; product. We provide ALL the source code
for your convenience and to
13 00000000 ; help you experience uC/CPU. The fact th
at the source code is provided
14 00000000 ; does NOT mean that you can use it withou
t paying a licensing fee.
15 00000000 ;
16 00000000 ; Knowledge of the source code may NOT be
used to develop a similar product.
17 00000000 ;
18 00000000 ; Please help us continue to provide the E
mbedded community with the finest
19 00000000 ; software available. Your honesty is gre
atly appreciated.
20 00000000 ;*******************************************************
*************************************************
21 00000000
22 00000000 ;*******************************************************
*************************************************
23 00000000 ;
24 00000000 ; CPU PORT FI
LE
25 00000000 ;
26 00000000 ; ARM
27 00000000 ; Keil uVision with the ARM Real
View Compiler (RVMDK)
28 00000000 ;
29 00000000 ; Filename : cpu_a.s
30 00000000 ; Version : V1.16
31 00000000 ; Programmer(s) : JJL
32 00000000 ; JDH
33 00000000 ; ITJ
34 00000000 ;*******************************************************
*************************************************
35 00000000
36 00000000
37 00000000 ;*******************************************************
*************************************************
38 00000000 ; PUBLIC FUNCT
IONS
39 00000000 ;*******************************************************
ARM Macro Assembler Page 2
*************************************************
40 00000000
41 00000000 EXPORT CPU_SR_Save
42 00000000 EXPORT CPU_SR_Restore
43 00000000
44 00000000
45 00000000 ;*******************************************************
*************************************************
46 00000000 ; EQUATES
47 00000000 ;*******************************************************
*************************************************
48 00000000
49 00000000 000000C0
CPU_ARM_CTRL_INT_DIS
EQU 0xC0 ; Disable both FIQ
& IRQ
50 00000000
51 00000000
52 00000000 ;*******************************************************
*************************************************
53 00000000 ; CODE GENERATION D
IRECTIVES
54 00000000 ;*******************************************************
*************************************************
55 00000000
56 00000000 AREA _CPU_A_CODE_, CODE, READONLY
57 00000000 ARM
58 00000000
59 00000000
60 00000000 ;$PAGE
61 00000000 ;*******************************************************
*************************************************
62 00000000 ; CRITICAL SECTION
FUNCTIONS
63 00000000 ;
64 00000000 ; Description : Disable/Enable interrupts by preserving
the state of interrupts. Generally speaking, the
65 00000000 ; state of the interrupt disable flag is s
tored in the local variable 'cpu_sr' & interrupts
66 00000000 ; are then disabled ('cpu_sr' is allocated
in all functions that need to disable interrupts).
67 00000000 ; The previous interrupt state is restored
by copying 'cpu_sr' into the CPU's status register.
68 00000000 ;
69 00000000 ; Prototypes : CPU_SR CPU_SR_Save(void);
70 00000000 ; void CPU_SR_Restore(CPU_SR cpu_sr);
71 00000000 ;
72 00000000 ; Note(s) : (1) These functions are used in general
like this :
73 00000000 ;
74 00000000 ; void Task (void *p_arg)
75 00000000 ; {
76 00000000 ;
/* Allocate storage for CPU status register */
77 00000000 ; #if (CPU_CFG_CRITICAL_METHOD ==
CPU_CRITICAL_METHOD_STATUS_LOCAL)
78 00000000 ; CPU_SR cpu_sr;
79 00000000 ; #endif
ARM Macro Assembler Page 3
80 00000000 ;
81 00000000 ; :
82 00000000 ; :
83 00000000 ; CPU_CRITICAL_ENTER();
/* cpu_sr = CPU_SR_Save(); */
84 00000000 ; :
85 00000000 ; :
86 00000000 ; CPU_CRITICAL_EXIT();
/* CPU_SR_Restore(cpu_sr); */
87 00000000 ; :
88 00000000 ; :
89 00000000 ; }
90 00000000 ;
91 00000000 ; (2) CPU_SR_Restore() is implemented as r
ecommended by Atmel's application note :
92 00000000 ;
93 00000000 ; "Disabling Interrupts at Process
or Level"
94 00000000 ;*******************************************************
*************************************************
95 00000000
96 00000000 CPU_SR_Save
97 00000000 E10F0000 MRS R0, CPSR
98 00000004
99 00000004 CPU_SR_Save_Loop
100 00000004 ; Set IRQ & FIQ bits in CPSR to DISABLE all interrupts
101 00000004 E38010C0 ORR R1, R0, #CPU_ARM_CTRL_INT_DIS
102 00000008 E121F001 MSR CPSR_c, R1
103 0000000C E10F1000 MRS R1, CPSR ; Confirm that CPSR
contains the prope
r interrupt disable
flags
104 00000010 E20110C0 AND R1, R1, #CPU_ARM_CTRL_INT_DIS
105 00000014 E35100C0 CMP R1, #CPU_ARM_CTRL_INT_DIS
106 00000018 1AFFFFF9 BNE CPU_SR_Save_Loop ; NOT properly
DISABLED (try agai
n)
107 0000001C E12FFF1E BX LR ; DISABLED, return
the original CPSR c
ontents in R0
108 00000020
109 00000020
110 00000020 CPU_SR_Restore ; See Note #2
111 00000020 E121F000 MSR CPSR_c, R0
112 00000024 E12FFF1E BX LR
113 00000028
114 00000028
115 00000028 END
Command Line: --debug --xref --device=DARMP --apcs=interwork -o.\cpu_a.o -Id:\K
eil\ARM\INC\Philips --list=.\Flash\cpu_a.lst ..\..\..\..\..\uC-CPU\ARM\RVMDK\cp
u_a.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
CPU_SR_Restore 00000020
Symbol: CPU_SR_Restore
Definitions
At line 110 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Uses
At line 42 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Comment: CPU_SR_Restore used once
CPU_SR_Save 00000000
Symbol: CPU_SR_Save
Definitions
At line 96 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Uses
At line 41 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Comment: CPU_SR_Save used once
CPU_SR_Save_Loop 00000004
Symbol: CPU_SR_Save_Loop
Definitions
At line 99 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Uses
At line 106 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Comment: CPU_SR_Save_Loop used once
_CPU_A_CODE_ 00000000
Symbol: _CPU_A_CODE_
Definitions
At line 56 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Uses
None
Comment: _CPU_A_CODE_ unused
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.debug_info$$$_CPU_A_CODE_ 00000000
Symbol: .debug_info$$$_CPU_A_CODE_
Definitions
None
Uses
None
Warning: .debug_info$$$_CPU_A_CODE_ undefinedComment: .debug_info$$$_CPU_A_CODE
_ unused
1 symbol
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.debug_line$$$_CPU_A_CODE_ 00000000
Symbol: .debug_line$$$_CPU_A_CODE_
Definitions
None
Uses
None
Warning: .debug_line$$$_CPU_A_CODE_ undefinedComment: .debug_line$$$_CPU_A_CODE
_ unused
1 symbol
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.debug_abbrev 00000000
Symbol: .debug_abbrev
Definitions
None
Uses
None
Warning: .debug_abbrev undefinedComment: .debug_abbrev unused
__ARM_asm.debug_abbrev 00000000
Symbol: __ARM_asm.debug_abbrev
Definitions
None
Uses
None
Warning: __ARM_asm.debug_abbrev undefinedComment: __ARM_asm.debug_abbrev unused
2 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
CPU_ARM_CTRL_INT_DIS 000000C0
Symbol: CPU_ARM_CTRL_INT_DIS
Definitions
At line 49 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
Uses
At line 101 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
At line 104 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
At line 105 in file ..\..\..\..\..\uC-CPU\ARM\RVMDK\cpu_a.s
1 symbol
328 symbols in table
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