📄 os_viewc.lst
字号:
108 * Returns ; none.
109 *
110 * Note(s) : 1) This function assumes that a free running timer has been initialized. The timer can
111 * either be a 16 bits or 32 bits timer. Your application needs to provide a function
112 * called OSView_TmrRd() that reads the current counts of this timer. The free running
113 * timer is initialized by the BSP function OSView_TmrInit().
114 *********************************************************************************************************
115 */
116
\ In segment CODE, align 4, keep-with-next
117 void OSView_InitTarget (INT32U baud_rate)
118 {
\ OSView_InitTarget:
\ 00000000 F0402DE9 PUSH {R4-R7,LR}
\ 00000004 0050B0E1 MOVS R5,R0
119 INT16U div; /* Baud rate divisor */
120 INT8U divlo;
121 INT8U divhi;
122 INT8U lcr; /* Line Control Register */
123 INT32U p_clk_freq;
124 INT32U pinsel;
125
126
127 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
128 OS_CPU_SR cpu_sr = 0;
\ 00000008 0040A0E3 MOV R4,#+0
129 #endif
130
131
132 OSView_TmrInit(); /* Initialize the free running timer */
\ 0000000C ........ _BLF OSView_TmrInit,??OSView_TmrInit??rA
133
134 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
135 /* Compute divisor for desired baud rate */
136 p_clk_freq = BSP_CPU_PclkFreq(PCLK_UART0); /* Get the CPU clock frequency */
137
138 div = (INT16U)(((2 * p_clk_freq / 16 / baud_rate) + 1) / 2);
139 divlo = div & 0x00FF; /* Split divisor into LOW and HIGH bytes */
140 divhi = (div >> 8) & 0x00FF;
141 lcr = 0x03; /* 8 Bits, 1 Stop, No Parity */
142
143 OS_ENTER_CRITICAL();
144 /* Configure P0.2 & P0.3 for UART0 */
145 pinsel = PINSEL0;
146 pinsel &= 0xFFFFFF0F;
147 pinsel |= 0x00000050;
148 PINSEL0 = pinsel;
149
150 U0LCR = DEF_BIT_07; /* Set divisor access bit */
151 U0DLL = divlo; /* Load divisor */
152 U0DLM = divhi;
153 U0LCR = lcr; /* Set line control register (Bit 8 is 0) */
154 U0IER = 0x00; /* Disable both Rx and Tx interrupts */
155 U0FCR = 0x07; /* Enable FIFO, flush Rx & Tx */
156 OS_EXIT_CRITICAL();
157 /* VIC UART #1 Initialization */
158 VICIntSelect &= ~(1 << VIC_UART0); /* Enable interrupts */
159 VICVectAddr6 = (INT32U)OSView_RxTxISRHandler; /* Set the vector address */
160 VICIntEnable = (1 << VIC_UART0); /* Enable Interrupts */
161 #endif
162
163
164
165 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
166 /* Compute divisor for desired baud rate */
167 p_clk_freq = BSP_CPU_PclkFreq(PCLK_UART1); /* Get the CPU clock frequency */
\ 00000010 0400A0E3 MOV R0,#+4
\ 00000014 ........ _BLF BSP_CPU_PclkFreq,??BSP_CPU_PclkFreq??rA
168
169 div = (INT16U)(((2 * p_clk_freq / 16 / baud_rate) + 1) / 2);
\ 00000018 0210A0E3 MOV R1,#+2
\ 0000001C 910010E0 MULS R0,R1,R0
\ 00000020 2002B0E1 LSRS R0,R0,#+4
\ 00000024 0510B0E1 MOVS R1,R5
\ 00000028 ........ _BLF ??divu32_a,??rA??divu32_a
\ 0000002C 010091E2 ADDS R0,R1,#+1
\ 00000030 A000B0E1 LSRS R0,R0,#+1
170 divlo = div & 0x00FF; /* Split divisor into LOW and HIGH bytes */
\ 00000034 0050B0E1 MOVS R5,R0
171 divhi = (div >> 8) & 0x00FF;
\ 00000038 2064B0E1 LSRS R6,R0,#+8
172 lcr = 0x03; /* 8 Bits, 1 Stop, No Parity */
\ 0000003C 0370A0E3 MOV R7,#+3
173
174 OS_ENTER_CRITICAL();
\ 00000040 ........ _BLF OS_CPU_SR_Save,??OS_CPU_SR_Save??rA
\ 00000044 0040B0E1 MOVS R4,R0
175 /* Configure P3.16 & P3.17 for UART1 */
176 pinsel = PINSEL7;
\ 00000048 B0009FE5 LDR R0,??OSView_InitTarget_0 ;; 0xffffffffe002c01c
\ 0000004C 000090E5 LDR R0,[R0, #+0]
177 pinsel &= 0xFFFFFFF0;
\ 00000050 0F00D0E3 BICS R0,R0,#0xF
178 pinsel |= 0x0000000F;
\ 00000054 0F0090E3 ORRS R0,R0,#0xF
179 PINSEL7 = pinsel;
\ 00000058 A0109FE5 LDR R1,??OSView_InitTarget_0 ;; 0xffffffffe002c01c
\ 0000005C 000081E5 STR R0,[R1, #+0]
180
181 U1LCR = DEF_BIT_07; /* Set divisor access bit */
\ 00000060 CE02A0E3 MOV R0,#-536870900
\ 00000064 400B80E3 ORR R0,R0,#0x10000
\ 00000068 8010A0E3 MOV R1,#+128
\ 0000006C 0010C0E5 STRB R1,[R0, #+0]
182 U1DLL = divlo; /* Load divisor */
\ 00000070 E004A0E3 MOV R0,#-536870912
\ 00000074 400B80E3 ORR R0,R0,#0x10000
\ 00000078 0050C0E5 STRB R5,[R0, #+0]
183 U1DLM = divhi;
\ 0000007C 4E02A0E3 MOV R0,#-536870908
\ 00000080 400B80E3 ORR R0,R0,#0x10000
\ 00000084 FF6016E2 ANDS R6,R6,#0xFF ;; Zero extend
\ 00000088 006080E5 STR R6,[R0, #+0]
184 U1LCR = lcr; /* Set line control register (Bit 8 is 0) */
\ 0000008C CE02A0E3 MOV R0,#-536870900
\ 00000090 400B80E3 ORR R0,R0,#0x10000
\ 00000094 0070C0E5 STRB R7,[R0, #+0]
185 U1IER = 0x00; /* Disable both Rx and Tx interrupts */
\ 00000098 4E02A0E3 MOV R0,#-536870908
\ 0000009C 400B80E3 ORR R0,R0,#0x10000
\ 000000A0 0010A0E3 MOV R1,#+0
\ 000000A4 001080E5 STR R1,[R0, #+0]
186 U1FCR = 0x07; /* Enable FIFO, flush Rx & Tx */
\ 000000A8 8E02A0E3 MOV R0,#-536870904
\ 000000AC 400B80E3 ORR R0,R0,#0x10000
\ 000000B0 0710A0E3 MOV R1,#+7
\ 000000B4 001080E5 STR R1,[R0, #+0]
187 OS_EXIT_CRITICAL();
\ 000000B8 0400B0E1 MOVS R0,R4
\ 000000BC ........ _BLF OS_CPU_SR_Restore,??OS_CPU_SR_Restore??rA
188 /* VIC UART #1 Initialization */
189 VICIntSelect &= ~(1 << VIC_UART1); /* Enable interrupts */
\ 000000C0 F300E0E3 MVN R0,#+243
\ 000000C4 F00EC0E3 BIC R0,R0,#0xF00
\ 000000C8 F310E0E3 MVN R1,#+243
\ 000000CC F01EC1E3 BIC R1,R1,#0xF00
\ 000000D0 001091E5 LDR R1,[R1, #+0]
\ 000000D4 8010D1E3 BICS R1,R1,#0x80
\ 000000D8 001080E5 STR R1,[R0, #+0]
190 VICVectAddr7 = (INT32U)OSView_RxTxISRHandler; /* Set the vector address */
\ 000000DC E300E0E3 MVN R0,#+227
\ 000000E0 E00EC0E3 BIC R0,R0,#0xE00
\ 000000E4 18109FE5 LDR R1,??OSView_InitTarget_0+0x4 ;; OSView_RxTxISRHandler
\ 000000E8 001080E5 STR R1,[R0, #+0]
191 VICIntEnable = (1 << VIC_UART1); /* Enable Interrupts */
\ 000000EC EF00E0E3 MVN R0,#+239
\ 000000F0 F00EC0E3 BIC R0,R0,#0xF00
\ 000000F4 8010A0E3 MOV R1,#+128
\ 000000F8 001080E5 STR R1,[R0, #+0]
192 #endif
193 }
\ 000000FC F080BDE8 POP {R4-R7,PC} ;; return
\ ??OSView_InitTarget_0:
\ 00000100 1CC002E0 DC32 0xffffffffe002c01c
\ 00000104 ........ DC32 OSView_RxTxISRHandler
194
195 /*
196 *********************************************************************************************************
197 * Disable & Enable Rx Interrupts
198 *
199 * Description: These functions enable and disable the Rx interrupt.
200 *
201 * Arguments : none
202 *
203 * Returns : none
204 *********************************************************************************************************
205 */
206
\ In segment CODE, align 4, keep-with-next
207 void OSView_RxIntDis (void)
208 {
209 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
210 U0IER = 0;
211 #endif
212
213 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
214 U1IER = 0;
\ OSView_RxIntDis:
\ 00000000 4E02A0E3 MOV R0,#-536870908
\ 00000004 400B80E3 ORR R0,R0,#0x10000
\ 00000008 0010A0E3 MOV R1,#+0
\ 0000000C 001080E5 STR R1,[R0, #+0]
215 #endif
216 }
\ 00000010 0EF0A0E1 MOV PC,LR ;; return
217
\ In segment CODE, align 4, keep-with-next
218 void OSView_RxIntEn (void)
219 {
220 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_0
221 U0IER = DEF_BIT_00;
222 #endif
223
224 #if OS_VIEW_COMM_SEL == OS_VIEW_UART_1
225 U1IER = DEF_BIT_00;
\ OSView_RxIntEn:
\ 00000000 4E02A0E3 MOV R0,#-536870908
\ 00000004 400B80E3 ORR R0,R0,#0x10000
\ 00000008 0110A0E3 MOV R1,#+1
\ 0000000C 001080E5 STR R1,[R0, #+0]
226 #endif
227 }
\ 00000010 0EF0A0E1 MOV PC,LR ;; return
228
229 /*
230 *********************************************************************************************************
231 * Rx & Tx Communication handler for uC/OS-View
232 *
233 * Note(s) : This adaptation of uC/OS-View assumes that a 'combined' interrupt is generated by the UART
234 * and thus these functions need not be populated.
235 *********************************************************************************************************
236 */
237
\ In segment CODE, align 4, keep-with-next
238 void OSView_RxISRHandler (void)
239 {
240 ;
241 }
\ OSView_RxISRHandler:
\ 00000000 0EF0A0E1 MOV PC,LR ;; return
242
\ In segment CODE, align 4, keep-with-next
243 void OSView_TxISRHandler (void)
244 {
245 ;
246 }
\ OSView_TxISRHandler:
\ 00000000 0EF0A0E1 MOV PC,LR ;; return
247
248
249 /*
250 *********************************************************************************************************
251 * Rx/Tx Communication handler for uC/OS-View ('combined' interrupt handler)
252 *
253 * Description: The Rx/Tx ISR handler.
254 *
255 * Arguments : none.
256 *
257 * Returns : none
258 *********************************************************************************************************
259 */
260
\ In segment CODE, align 4, keep-with-next
261 void OSView_RxTxISRHandler (void)
262 {
\ OSView_RxTxISRHandler:
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -