📄 bsp.lst
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255 break;
256
257 case 1:
258 fin = MAIN_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_4:
\ 00000034 B708A0E3 MOV R0,#+11993088
\ 00000038 6C0D80E3 ORR R0,R0,#0x1B00
\ 0000003C 030000EA B ??BSP_CPU_ClkFreq_3
259 break;
260
261 case 2:
262 fin = RTC_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_5:
\ 00000040 800CA0E3 MOV R0,#+32768
\ 00000044 010000EA B ??BSP_CPU_ClkFreq_3
263 break;
264
265 default:
266 fin = IRC_OSC_FRQ;
\ ??BSP_CPU_ClkFreq_1:
\ 00000048 B708A0E3 MOV R0,#+11993088
\ 0000004C 6C0D80E3 ORR R0,R0,#0x1B00
267 break;
268 }
269
270 if ((PLLSTAT & (1 << 25)) > 0) { /* If the PLL is currently enabled and connected */
\ ??BSP_CPU_ClkFreq_3:
\ 00000050 ........ LDR R1,??DataTable15 ;; 0xffffffffe01fc088
\ 00000054 001091E5 LDR R1,[R1, #+0]
\ 00000058 800711E3 TST R1,#0x2000000
\ 0000005C 0F00000A BEQ ??BSP_CPU_ClkFreq_6
271 msel = (CPU_INT32U)(PLLSTAT & 0x3FFF) + 1; /* Obtain the PLL multiplier */
\ 00000060 ........ LDR R1,??DataTable15 ;; 0xffffffffe01fc088
\ 00000064 001091E5 LDR R1,[R1, #+0]
\ 00000068 0119B0E1 LSLS R1,R1,#+18
\ 0000006C 0120A0E3 MOV R2,#+1
\ 00000070 212992E0 ADDS R2,R2,R1, LSR #+18
272 nsel = (CPU_INT32U)((PLLSTAT >> 16) & 0x0F) + 1; /* Obtain the PLL divider */
\ 00000074 ........ LDR R1,??DataTable15 ;; 0xffffffffe01fc088
\ 00000078 001091E5 LDR R1,[R1, #+0]
\ 0000007C 0F30A0E3 MOV R3,#+15
\ 00000080 211813E0 ANDS R1,R3,R1, LSR #+16
\ 00000084 011091E2 ADDS R1,R1,#+1
273 pll_clk_feq = (2 * msel * fin / nsel); /* Compute the PLL output frequency */
\ 00000088 900212E0 MULS R2,R0,R2
\ 0000008C 0230A0E3 MOV R3,#+2
\ 00000090 930210E0 MULS R0,R3,R2
\ 00000094 ........ _BLF ??divu32_a,??rA??divu32_a
\ 00000098 0100B0E1 MOVS R0,R1
\ 0000009C FFFFFFEA B ??BSP_CPU_ClkFreq_7
274 } else {
275 pll_clk_feq = (fin); /* The PLL is bypassed */
276 }
277
278 clk_div = (CPU_INT08U)(CCLKCFG & 0x0F) + 1; /* Obtain the CPU core clock divider */
\ ??BSP_CPU_ClkFreq_6:
\ ??BSP_CPU_ClkFreq_7:
\ 000000A0 ........ LDR R1,??DataTable11 ;; 0xffffffffe01fc104
\ 000000A4 001091E5 LDR R1,[R1, #+0]
\ 000000A8 0F1011E2 ANDS R1,R1,#0xF
\ 000000AC 011091E2 ADDS R1,R1,#+1
279 clk_freq = (CPU_INT32U)(pll_clk_feq / clk_div); /* Compute the ARM Core clock frequency */
\ 000000B0 ........ _BLF ??divu32_a,??rA??divu32_a
\ 000000B4 0100B0E1 MOVS R0,R1
280
281 return (clk_freq);
\ 000000B8 0080BDE8 POP {PC} ;; return
282 }
283
284 /*
285 *********************************************************************************************************
286 * Get a Peripheral Clock Frequency
287 *
288 * Description : This function reads CPU registers to determine the the clock frequency for the specified
289 * peripheral
290 *
291 * Arguements : An ID, one of PCLK_??? defined in bsp.c
292 *
293 * Returns : The peripheral's clock in Hz
294 *********************************************************************************************************
295 */
296
297
\ In segment CODE, align 4, keep-with-next
298 CPU_INT32U BSP_CPU_PclkFreq (CPU_INT08U pclk)
299 {
\ BSP_CPU_PclkFreq:
\ 00000000 10402DE9 PUSH {R4,LR}
\ 00000004 0040B0E1 MOVS R4,R0
300 CPU_INT32U clk_freq;
301 CPU_INT32U selection;
302
303
304 clk_freq = BSP_CPU_ClkFreq();
\ 00000008 ........ BL BSP_CPU_ClkFreq
305
306 switch (pclk) {
\ 0000000C 0410B0E1 MOVS R1,R4
\ 00000010 1D0051E3 CMP R1,#+29
\ 00000014 2F00008A BHI ??BSP_CPU_PclkFreq_1
\ 00000018 012F8FE2 ADR R2,??BSP_CPU_PclkFreq_0
\ 0000001C 0120D2E7 LDRB R2,[R2, R1]
\ 00000020 02F18FE0 ADD PC,PC,R2, LSL #+2
\ ??BSP_CPU_PclkFreq_0:
\ 00000024 07070707 DC8 +7,+7,+7,+7
\ 00000028 07070707 DC8 +7,+7,+7,+7
\ 0000002C 07070707 DC8 +7,+7,+7,+7
\ 00000030 07070707 DC8 +7,+7,+7,+7
\ 00000034 19191919 DC8 +25,+25,+25,+25
\ 00000038 2C191919 DC8 +44,+25,+25,+25
\ 0000003C 19191919 DC8 +25,+25,+25,+25
\ 00000040 2C190000 DC8 +44,+25,+0,+0
307 case PCLK_WDT:
308 case PCLK_TIMER0:
309 case PCLK_TIMER1:
310 case PCLK_UART0:
311 case PCLK_UART1:
312 case PCLK_PWM0:
313 case PCLK_PWM1:
314 case PCLK_I2C0:
315 case PCLK_SPI:
316 case PCLK_RTC:
317 case PCLK_SSP1:
318 case PCLK_DAC:
319 case PCLK_ADC:
320 case PCLK_CAN1:
321 case PCLK_CAN2:
322 case PCLK_ACF:
323 selection = ((PCLKSEL0 >> (pclk * 2)) & 0x03);
\ ??BSP_CPU_PclkFreq_2:
\ 00000044 ........ LDR R1,??DataTable13 ;; 0xffffffffe01fc1a8
\ 00000048 001091E5 LDR R1,[R1, #+0]
\ 0000004C 0220A0E3 MOV R2,#+2
\ 00000050 920413E0 MULS R3,R2,R4
\ 00000054 0320A0E3 MOV R2,#+3
\ 00000058 311312E0 ANDS R1,R2,R1, LSR R3
324 if (selection == 0) {
\ 0000005C 000051E3 CMP R1,#+0
\ 00000060 0100001A BNE ??BSP_CPU_PclkFreq_3
325 return (clk_freq / 4);
\ 00000064 2001B0E1 LSRS R0,R0,#+2
\ 00000068 1B0000EA B ??BSP_CPU_PclkFreq_4
326 } else if (selection == 1) {
\ ??BSP_CPU_PclkFreq_3:
\ 0000006C 010051E3 CMP R1,#+1
\ 00000070 1900000A BEQ ??BSP_CPU_PclkFreq_4
327 return (clk_freq);
328 } else if (selection == 2) {
\ ??BSP_CPU_PclkFreq_5:
\ 00000074 020051E3 CMP R1,#+2
\ 00000078 0100001A BNE ??BSP_CPU_PclkFreq_6
329 return (clk_freq / 2);
\ 0000007C A000B0E1 LSRS R0,R0,#+1
\ 00000080 150000EA B ??BSP_CPU_PclkFreq_4
330 } else {
331 return (clk_freq / 8);
\ ??BSP_CPU_PclkFreq_6:
\ 00000084 A001B0E1 LSRS R0,R0,#+3
\ 00000088 130000EA B ??BSP_CPU_PclkFreq_4
332 }
333
334 case PCLK_BAT_RAM:
335 case PCLK_GPIO:
336 case PCLK_PCB:
337 case PCLK_I2C1:
338 case PCLK_SSP0:
339 case PCLK_TIMER2:
340 case PCLK_TIMER3:
341 case PCLK_UART2:
342 case PCLK_UART3:
343 case PCLK_I2C2:
344 case PCLK_MCI:
345 case PCLK_SYSCON:
346 selection = ((PCLKSEL1 >> ((pclk - 16) * 2)) & 0x03);
\ ??BSP_CPU_PclkFreq_7:
\ 0000008C ........ LDR R1,??DataTable14 ;; 0xffffffffe01fc1ac
\ 00000090 001091E5 LDR R1,[R1, #+0]
\ 00000094 F02094E2 ADDS R2,R4,#+240
\ 00000098 0230A0E3 MOV R3,#+2
\ 0000009C 930212E0 MULS R2,R3,R2
\ 000000A0 0330A0E3 MOV R3,#+3
\ 000000A4 311213E0 ANDS R1,R3,R1, LSR R2
347 if (selection == 0) {
\ 000000A8 000051E3 CMP R1,#+0
\ 000000AC 0100001A BNE ??BSP_CPU_PclkFreq_8
348 return (clk_freq / 4);
\ 000000B0 2001B0E1 LSRS R0,R0,#+2
\ 000000B4 080000EA B ??BSP_CPU_PclkFreq_4
349 } else if (selection == 1) {
\ ??BSP_CPU_PclkFreq_8:
\ 000000B8 010051E3 CMP R1,#+1
\ 000000BC 0600000A BEQ ??BSP_CPU_PclkFreq_4
350 return (clk_freq);
351 } else if (selection == 2) {
\ ??BSP_CPU_PclkFreq_9:
\ 000000C0 020051E3 CMP R1,#+2
\ 000000C4 0100001A BNE ??BSP_CPU_PclkFreq_10
352 return (clk_freq / 2);
\ 000000C8 A000B0E1 LSRS R0,R0,#+1
\ 000000CC 020000EA B ??BSP_CPU_PclkFreq_4
353 } else {
354 return (clk_freq / 8);
\ ??BSP_CPU_PclkFreq_10:
\ 000000D0 A001B0E1 LSRS R0,R0,#+3
\ 000000D4 000000EA B ??BSP_CPU_PclkFreq_4
355 }
356
357 default:
358 return (0);
\ ??BSP_CPU_PclkFreq_1:
\ 000000D8 0000A0E3 MOV R0,#+0
\ ??BSP_CPU_PclkFreq_4:
\ 000000DC 1080BDE8 POP {R4,PC} ;; return
359 }
360 }
361
362 /*
363 *********************************************************************************************************
364 * DISABLE ALL INTERRUPTS
365 *
366 * Description : This function disables all interrupts from the interrupt controller.
367 *
368 * Arguments : none
369 *
370 * Returns : None
371 *********************************************************************************************************
372 */
373
\ In segment CODE, align 4, keep-with-next
374 void BSP_IntDisAll (void)
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