📄 os_dcc.lst
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\ In segment CODE, align 4, keep-with-next
102 static __arm INT32U OSDCC_Read (void)
103 {
104 __asm("mrc P14,0,R0,C1,C0");
\ OSDCC_Read:
\ 00000000 100E11EE mrc P14,0,R0,C1,C0
105 }
\ 00000004 0EF0A0E1 MOV PC,LR ;; return
106
107 /*
108 *********************************************************************************************************
109 * OSDCC_Write()
110 *
111 * Description: This function places data in the comms data write register.
112 *
113 * Arguments : none
114 *
115 * Returns : none
116 *********************************************************************************************************
117 */
118
\ In segment CODE, align 4, keep-with-next
119 static __arm void OSDCC_Write (INT32U data)
120 {
121 __asm("mcr P14,0,R0,C1,C0");
\ OSDCC_Write:
\ 00000000 100E01EE mcr P14,0,R0,C1,C0
122 }
\ 00000004 0EF0A0E1 MOV PC,LR ;; return
123
124 /*
125 *********************************************************************************************************
126 * OSDCC_Handler()
127 *
128 * Description: This function reads commands from the DCC comms data read register. Data may be
129 * transferred to or from memory based on those commands.
130 *
131 * Arguments : none
132 *
133 * Returns : none
134 *
135 * Notes : 1) This function should be called periodically. If OS_CPU_ARM_DCC_EN is '1', this
136 * function will be called from both the idle task hook and the tick interrupt hook.
137 *********************************************************************************************************
138 */
139
\ In segment CODE, align 4, keep-with-next
140 void OSDCC_Handler (void)
141 {
\ OSDCC_Handler:
\ 00000000 30402DE9 PUSH {R4,R5,LR}
142 INT32U reg_val;
143 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
144 OS_CPU_SR cpu_sr = 0;
\ 00000004 0000A0E3 MOV R0,#+0
\ 00000008 0050B0E1 MOVS R5,R0
145 #endif
146
147
148 OS_ENTER_CRITICAL(); /* Disable interrupts */
\ 0000000C ........ _BLF OS_CPU_SR_Save,??OS_CPU_SR_Save??rA
\ 00000010 0050B0E1 MOVS R5,R0
149
150 /* Check for the presence of new data */
151 if ((OSDCC_ReadCtrl() & OS_DCC_COMM_CTRL_RD) != 0) {
\ 00000014 ........ BL OSDCC_ReadCtrl
\ 00000018 010010E3 TST R0,#0x1
\ 0000001C 5C00000A BEQ ??OSDCC_Handler_0
152 reg_val = OSDCC_Read(); /* Read the new data */
\ 00000020 ........ BL OSDCC_Read
\ 00000024 0040B0E1 MOVS R4,R0
153
154 if ((reg_val & OS_DCC_OP_COMMAND) != 0) { /* Determine whether a command has been received */
\ 00000028 010014E3 TST R4,#0x1
\ 0000002C 5600000A BEQ ??OSDCC_Handler_1
155 OSDCC_Cmd = reg_val;
\ 00000030 44029FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 00000034 004080E5 STR R4,[R0, #+0]
156 /* Check for an odd address in the next operation */
157 if ((OSDCC_Cmd & OS_DCC_OP_ODD_ADDR) != 0) {
\ 00000038 3C029FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 0000003C 000090E5 LDR R0,[R0, #+0]
\ 00000040 800410E3 TST R0,#0x80000000
\ 00000044 0400000A BEQ ??OSDCC_Handler_3
158 OSDCC_Addr |= 1;
\ 00000048 30029FE5 LDR R0,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 0000004C 2C129FE5 LDR R1,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 00000050 001091E5 LDR R1,[R1, #+0]
\ 00000054 011091E3 ORRS R1,R1,#0x1
\ 00000058 001080E5 STR R1,[R0, #+0]
159 }
160 /* If data will be read, adjust OSDCC_ItemCnt */
161 if ((OSDCC_Cmd & (OS_DCC_OP_READ_U32 | OS_DCC_OP_READ_U16 | OS_DCC_OP_READ_U8
162 | OS_DCC_OP_GET_CAPS)) != 0) {
\ ??OSDCC_Handler_3:
\ 0000005C 18029FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 00000060 000090E5 LDR R0,[R0, #+0]
\ 00000064 F00610E3 TST R0,#0xF000000
\ 00000068 0600000A BEQ ??OSDCC_Handler_4
163 OSDCC_ItemCnt = (OSDCC_Cmd >> 2) & 0xffff;
\ 0000006C 10029FE5 LDR R0,??OSDCC_Handler_2+0x8 ;; OSDCC_ItemCnt
\ 00000070 04129FE5 LDR R1,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 00000074 001091E5 LDR R1,[R1, #+0]
\ 00000078 0117B0E1 LSLS R1,R1,#+14
\ 0000007C 2118B0E1 LSRS R1,R1,#+16
\ 00000080 001080E5 STR R1,[R0, #+0]
\ 00000084 3D0000EA B ??OSDCC_Handler_5
164 } else { /* Data will be written; initialize OSDCC_Data */
165 if ((OSDCC_Cmd & OS_DCC_OP_WRITE_U32) != 0) {
\ ??OSDCC_Handler_4:
\ 00000088 EC019FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 0000008C 000090E5 LDR R0,[R0, #+0]
\ 00000090 400510E3 TST R0,#0x10000000
\ 00000094 0900000A BEQ ??OSDCC_Handler_6
166 OSDCC_Data |= (OSDCC_Cmd << 14) & 0xffff0000;
\ 00000098 E8019FE5 LDR R0,??OSDCC_Handler_2+0xC ;; OSDCC_Data
\ 0000009C E4119FE5 LDR R1,??OSDCC_Handler_2+0xC ;; OSDCC_Data
\ 000000A0 001091E5 LDR R1,[R1, #+0]
\ 000000A4 D0219FE5 LDR R2,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 000000A8 002092E5 LDR R2,[R2, #+0]
\ 000000AC 0227B0E1 LSLS R2,R2,#+14
\ 000000B0 2228B0E1 LSRS R2,R2,#+16
\ 000000B4 021891E1 ORRS R1,R1,R2, LSL #+16
\ 000000B8 001080E5 STR R1,[R0, #+0]
\ 000000BC 050000EA B ??OSDCC_Handler_7
167 } else {
168 OSDCC_Data = (OSDCC_Cmd >> 2) & 0xffff;
\ ??OSDCC_Handler_6:
\ 000000C0 C0019FE5 LDR R0,??OSDCC_Handler_2+0xC ;; OSDCC_Data
\ 000000C4 B0119FE5 LDR R1,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 000000C8 001091E5 LDR R1,[R1, #+0]
\ 000000CC 0117B0E1 LSLS R1,R1,#+14
\ 000000D0 2118B0E1 LSRS R1,R1,#+16
\ 000000D4 001080E5 STR R1,[R0, #+0]
169 }
170 /* Write a single byte */
171 if ((OSDCC_Cmd & OS_DCC_OP_WRITE_U8) != 0) {
\ ??OSDCC_Handler_7:
\ 000000D8 9C019FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 000000DC 000090E5 LDR R0,[R0, #+0]
\ 000000E0 400410E3 TST R0,#0x40000000
\ 000000E4 0900000A BEQ ??OSDCC_Handler_8
172 *(INT8U *)OSDCC_Addr = OSDCC_Data;
\ 000000E8 90019FE5 LDR R0,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 000000EC 000090E5 LDR R0,[R0, #+0]
\ 000000F0 90119FE5 LDR R1,??OSDCC_Handler_2+0xC ;; OSDCC_Data
\ 000000F4 001091E5 LDR R1,[R1, #+0]
\ 000000F8 0010C0E5 STRB R1,[R0, #+0]
173 OSDCC_Addr += 1;
\ 000000FC 7C019FE5 LDR R0,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 00000100 78119FE5 LDR R1,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 00000104 001091E5 LDR R1,[R1, #+0]
\ 00000108 011091E2 ADDS R1,R1,#+1
\ 0000010C 001080E5 STR R1,[R0, #+0]
174 }
175 /* Write two bytes */
176 if ((OSDCC_Cmd & OS_DCC_OP_WRITE_U16) != 0) {
\ ??OSDCC_Handler_8:
\ 00000110 64019FE5 LDR R0,??OSDCC_Handler_2 ;; OSDCC_Cmd
\ 00000114 000090E5 LDR R0,[R0, #+0]
\ 00000118 800510E3 TST R0,#0x20000000
\ 0000011C 0900000A BEQ ??OSDCC_Handler_9
177 *(INT16U *)OSDCC_Addr = OSDCC_Data;
\ 00000120 58019FE5 LDR R0,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 00000124 000090E5 LDR R0,[R0, #+0]
\ 00000128 58119FE5 LDR R1,??OSDCC_Handler_2+0xC ;; OSDCC_Data
\ 0000012C 001091E5 LDR R1,[R1, #+0]
\ 00000130 B010C0E1 STRH R1,[R0, #+0]
178 OSDCC_Addr += 2;
\ 00000134 44019FE5 LDR R0,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
\ 00000138 40119FE5 LDR R1,??OSDCC_Handler_2+0x4 ;; OSDCC_Addr
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