📄 alu.fit.rpt
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Fitter report for alu
Sun Nov 30 22:18:21 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. HardCopy II Device Resource Guide
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. I/O Bank Usage
10. All Package Pins
11. Output Pin Default Load For Reported TCO
12. Fitter Resource Utilization by Entity
13. Delay Chain Summary
14. Pad To Core Delay Chain Fanout
15. Non-Global High Fan-Out Signals
16. Interconnect Usage Summary
17. LAB Logic Elements
18. LAB Signals Sourced
19. LAB Signals Sourced Out
20. LAB Distinct Inputs
21. I/O Rules Summary
22. I/O Rules Details
23. I/O Rules Matrix
24. Fitter Device Options
25. Operating Settings and Conditions
26. Advanced Data - General
27. Advanced Data - Placement Preparation
28. Advanced Data - Placement
29. Advanced Data - Routing
30. Fitter Messages
31. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Fitter Summary ;
+-------------------------------+------------------------------------------+
; Fitter Status ; Successful - Sun Nov 30 22:18:20 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; alu ;
; Top-level Entity Name ; alu ;
; Family ; Stratix II ;
; Device ; EP2S15F484C3 ;
; Timing Models ; Final ;
; Logic utilization ; 2 % ;
; Combinational ALUTs ; 288 / 12,480 ( 2 % ) ;
; Dedicated logic registers ; 0 / 12,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 99 / 343 ( 29 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 419,328 ( 0 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; AUTO ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
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