alu.map.summary

来自「用veriloghdl写的alu程序」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Sun Nov 30 22:18:12 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : alu
Top-level Entity Name : alu
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 288
    Dedicated logic registers : 0
Total registers : 0
Total pins : 99
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0