alu.v

用veriloghdl写的alu程序

module alu(ALU_DA_I,ALU_DB_I,ALU_Func_I,ALU_DC_O);
input[31:0] ALU_DA_I;
input[31:0] ALU_DB_I;
input[2:0] ALU_Func_I;
output[31:0] ALU_DC_O;
wire[31:0] DA_No_Symbol,DB_No_Symbol;
wire[31:0] ALU_DC_O;
assign DA_No_Symbol=ALU_DA_I;
assign DB_No_Symbol=ALU_DB_I;

assign ALU_DC_O=
		(ALU_Func_I=='b000)?DA_No_Symbol+DB_No_Symbol:
		(ALU_Func_I=='b001)?DA_No_Symbol-DB_No_Symbol:
		(ALU_Func_I=='b010)?DA_No_Symbol<<DB_No_Symbol:
		(ALU_Func_I=='b011)?DA_No_Symbol>>DB_No_Symbol:
		(ALU_Func_I=='b100)?DA_No_Symbol&DB_No_Symbol:
		(ALU_Func_I=='b101)?DA_No_Symbol|DB_No_Symbol:
		(ALU_Func_I=='b110)?~(DA_No_Symbol|DB_No_Symbol):DA_No_Symbol^DB_No_Symbol;
		
endmodule