initmemory.s

在三星的S3C44B0X上移植的uCOSII2.80的源程序

;/*
;*********************************************************************************************************
;* 文件: InitMemory.S
;* 描述: 对 Memory Controller 进行初始化配置.
;* 编写: 深思 ([e-mail]).
;*********************************************************************************************************
;*/

        EXPORT  InitMemory

BWSCON  EQU     0x01c80000

        AREA    FInitMemory,CODE,READONLY
        CODE32

InitMemory
        LDR     R0,     =SMRDATA                        ; Memory Controller.
        LDMIA   R0,     {R1-R13}
        LDR     R0,     =BWSCON
        STMIA   R0,     {R1-R13}
        MOV     PC,     LR

;/*
;*********************************************************************************************************
; 下面对 bank 的配置直接影响到系统性能, 请仔细配置.
;*********************************************************************************************************
;*/

SMRDATA DATA                                            ; Memory Controller Data.

; BWSCON.
ST7         EQU     0       ; Not using UB/LB OF BANK7.
WS7         EQU     0       ; WAIT disable (Bank7).
DW7         EQU     1       ; 16-bit (Bank7).
ST6         EQU     0       ; Not using UB/LB OF BANK6.
WS6         EQU     0       ; WAIT disable (Bank6).
DW6         EQU     1       ; 16-bit (Bank6).
ST5         EQU     0       ; Not using UB/LB OF BANK5.
WS5         EQU     0       ; WAIT disable (Bank5).
DW5         EQU     0       ; 8-bit (Bank5).
ST4         EQU     0       ; Not using UB/LB OF BANK4.
WS4         EQU     0       ; WAIT disable (Bank4).
DW4         EQU     0       ; 8-bit (Bank4).
ST3         EQU     0       ; Not using UB/LB OF BANK3.
WS3         EQU     0       ; WAIT disable (Bank3).
DW3         EQU     0       ; 8-bit (Bank3).
ST2         EQU     0       ; Not using UB/LB OF BANK2.
WS2         EQU     0       ; WAIT disable (Bank2).
DW2         EQU     0       ; 8-bit (Bank2).
ST1         EQU     0       ; Not using UB/LB OF BANK1.
WS1         EQU     0       ; WAIT disable (Bank1).
DW1         EQU     0       ; 8-bit (Bank1).
DW0         EQU     1       ; 16-bit (Bank0).
ENDIAN      EQU     0       ; Little endian.
        DCD     ((ST7<<31)+(WS7<<30)+(DW7<<28)+(ST6<<27)+(WS6<<26)+(DW6<<24)+(ST5<<23)+(WS5<<22)+(DW5<<20)+(ST4<<19)+(WS4<<18)+(DW4<<16)+(ST3<<15)+(WS3<<14)+(DW3<<12)+(ST2<<11)+(WS2<<10)+(DW2<<8)+(ST1<<7)+(WS1<<6)+(DW1<<4)+(DW0<<1)+ENDIAN)

; When MCLK=66MHz,1clk=0.0152us=15.2ns.
; BANKCON0.
B0_Tacs	    EQU     0       ; Address set-up nGCSn 0clk
B0_Tcos	    EQU     0       ; Chip selection set-up nOE 0clk
B0_Tacc	    EQU     0x6     ; Access cycle 10clk ( 因为 SST39VF160 最大访问时间是 90ns).
B0_Toch	    EQU     0x0     ; Chip selection hold on nOE 0clk
B0_Tcah	    EQU     0x0     ; Address holding time after nGCSn 0clk
B0_Tpac	    EQU     0x0     ; Page mode access cycle @ page mode 0clk
B0_PMC      EQU     0x0     ; Page mode configuration normal(1data)
        DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Toch<<6)+(B0_Tcah<<4)+(B0_Tpac<<2)+(B0_PMC))	;GCS0

; BANKCON1.(parameter for USB PDIUSBD12).
B1_Tacs     EQU	0x3
B1_Tcos     EQU	0x3
B1_Tacc     EQU	0x7
B1_Toch     EQU	0x3
B1_Tcah     EQU	0x3
B1_Tpac     EQU	0x3
B1_PMC      EQU	0x0
        DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Toch<<6)+(B1_Tcah<<4)+(B1_Tpac<<2)+(B1_PMC))	;GCS1 

;Bank 2 parameter for IDE
B2_Tacs		EQU	0x3         ;4clk
B2_Tcos		EQU	0x3         ;4clk
B2_Tacc		EQU	0x7         ;14clk
B2_Toch		EQU	0x3         ;4clk
B2_Tcah		EQU	0x3         ;4clk
B2_Tpac		EQU	0x3         ;6clk
B2_PMC		EQU	0x0         ;normal(1data)
        DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Toch<<6)+(B2_Tcah<<4)+(B2_Tpac<<2)+(B2_PMC))	;GCS2

;Bank 3 parameter for NET RTL8019AS.
B3_Tacs     EQU	0x3
B3_Tcos     EQU	0x3
B3_Tacc     EQU	0x7
B3_Toch	    EQU	0x3
B3_Tcah     EQU	0x3
B3_Tpac     EQU	0x3
B3_PMC      EQU	0x0         ;normal(1data)
        DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Toch<<6)+(B3_Tcah<<4)+(B3_Tpac<<2)+(B3_PMC))	;GCS3

;Bank 4.
B4_Tacs		EQU	0x3         ;4clk
B4_Tcos		EQU	0x3         ;4clk
B4_Tacc		EQU	0x7         ;14clk
B4_Toch		EQU	0x3         ;4clk
B4_Tcah		EQU	0x3         ;4clk
B4_Tpac		EQU	0x3         ;6clk
B4_PMC		EQU	0x0         ;normal(1data)
        DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Toch<<6)+(B4_Tcah<<4)+(B4_Tpac<<2)+(B4_PMC))	;GCS4

;Bank 5 parameter
B5_Tacs		EQU	0x3         ;4clk
B5_Tcos		EQU	0x3         ;4clk
B5_Tacc		EQU	0x7         ;14clk
B5_Toch		EQU	0x3         ;4clk
B5_Tcah		EQU	0x3         ;4clk
B5_Tpac		EQU	0x3         ;6clk
B5_PMC		EQU	0x0         ;normal(1data)
        DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Toch<<6)+(B5_Tcah<<4)+(B5_Tpac<<2)+(B5_PMC))	;GCS5

;Bank 6 parameter
B6_MT		EQU	0x3         ;SDRAM
B6_Trcd		EQU	0x0         ;2clk
B6_SCAN		EQU	0x0         ;8bit
		DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	;GCS6

;Bank 7 parameter
B7_MT		EQU	0x3         ;SDRAM
B7_Trcd		EQU	0x0         ;2clk
B7_SCAN		EQU	0x0         ;8bit
		DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))	;GCS7

;REGRESH.
REFEN       EQU     1       ; Enable Refresh.
TREFMD      EQU     0       ; CBR/Auto Refresh.
Trp         EQU     2       ; 4 clock.
Trc         EQU     1       ; 5 clock
Tchr        EQU     2       ; 1 clock
REFCNT      EQU     1425
        DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

;BankSize.
SCLKEN      EQU     1       ; SCLK for reducing power consumption.
BK76MAP     EQU     6       ; 8M/8M
        DCD ((SCLKEN<<4)+BK76MAP)

;MRSRB6
B6WBL       EQU     0
B6TM        EQU     0
B6CL        EQU     3       ; 3 CLOCK.
B6BT        EQU     0
B6BL        EQU     0
        DCD ((B6WBL<<9)+(B6TM<<7)+(B6CL<<4)+(B6BT<<3)+B6BL)
;MRSRB7
B7WBL       EQU     0
B7TM        EQU     0
B7CL        EQU     3       ; 3 CLOCK.
B7BT        EQU     0
B7BL        EQU     0
        DCD ((B7WBL<<9)+(B7TM<<7)+(B7CL<<4)+(B7BT<<3)+B7BL)

;/*
;*********************************************************************************************************
        END
;*********************************************************************************************************
;*/