📄 fl_thesis_00_2phase.mdl
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SourceType "FIS"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
fis "dvrd"
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController q"
Ports [1, 1]
Position [465, 141, 525, 189]
BackgroundColor "lightBlue"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
fis "dvrq"
}
Block {
BlockType Mux
Name "Mux"
Ports [3, 1]
Position [595, 127, 600, 203]
ShowName off
Inputs "3"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux1"
Ports [2, 1]
Position [110, 117, 115, 193]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Scope
Name "Scope1"
Ports [4]
Position [880, 359, 930, 416]
Floating off
Location [6, 52, 1030, 737]
Open off
NumInputPorts "4"
List {
ListType AxesTitles
axes1 "Ke PWM Generator"
axes2 "dq Kompensasi dan 0"
axes3 "Sensor Tegangan Beban Sensitif dq [pu]"
axes4 "Selisih Tegangan dq [pu]"
}
YMin "-4~0~-0.5~-5.55112e-017"
YMax "4~4~0.9~0.7"
SaveToWorkspace on
SaveName "dq0"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Selector
Name "Selector"
Ports [1, 1]
Position [235, 337, 270, 363]
InputPortWidth "3"
IndexOptions "Index vector (dialog)"
Indices "[1 2]"
OutputSizes "1"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [275, 145, 295, 165]
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
OutDataTypeStr "Inherit: Inherit via internal rule"
}
Block {
BlockType Terminator
Name "Terminator"
Position [105, 398, 120, 412]
NamePlacement "alternate"
}
Block {
BlockType Terminator
Name "Terminator1"
Position [105, 438, 120, 452]
}
Block {
BlockType Reference
Name "abc_to_dq0\nTransformation"
Ports [2, 1]
Position [165, 330, 215, 370]
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib_extras/Measurements/abc_to_dq0\nTransformation"
SourceType "abc to dq0 Transformation"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Reference
Name "dq0_to_abc\nTransformation"
Ports [2, 1]
Position [655, 149, 720, 211]
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib_extras/Measurements/dq0_to_abc\nTransformation"
SourceType "dq0 to abc Transformation"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Scope
Name "dqi"
Ports [1]
Position [645, 71, 680, 109]
Floating off
Location [1, 52, 1025, 737]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "sinus referensi"
}
YMin "-1.25"
YMax "1.25"
SaveToWorkspace on
SaveName "dqi"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Scope
Name "dqp"
Ports [1]
Position [365, 66, 400, 104]
Floating off
Location [5, 52, 1029, 737]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "sinus referensi"
}
YMin "-1.25"
YMax "1.25"
SaveToWorkspace on
SaveName "dqp"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Constant
Name "dref"
Position [60, 124, 85, 146]
NamePlacement "alternate"
OutDataType "sfix(16)"
OutScaling "2^0"
SampleTime "1e-6"
}
Block {
BlockType Constant
Name "qref"
Position [60, 165, 85, 185]
Value "0"
OutDataType "sfix(16)"
OutScaling "2^0"
SampleTime "1e-6"
}
Block {
BlockType Outport
Name "Vcontrol"
Position [885, 173, 915, 187]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "V2"
SrcPort 1
DstBlock "abc_to_dq0\nTransformation"
DstPort 1
}
Line {
SrcBlock "Discrete\nVirtual PLL"
SrcPort 1
DstBlock "Terminator"
DstPort 1
}
Line {
SrcBlock "Discrete\nVirtual PLL"
SrcPort 3
DstBlock "Terminator1"
DstPort 1
}
Line {
SrcBlock "Discrete\nVirtual PLL"
SrcPort 2
Points [60, 0]
Branch {
Labels [1, 0]
Points [0, -65]
DstBlock "abc_to_dq0\nTransformation"
DstPort 2
}
Branch {
Points [495, 0; 0, -230]
DstBlock "dq0_to_abc\nTransformation"
DstPort 2
}
}
Line {
SrcBlock "abc_to_dq0\nTransformation"
SrcPort 1
DstBlock "Selector"
DstPort 1
}
Line {
SrcBlock "Selector"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Sum"
DstPort 2
}
Branch {
Points [0, 45]
DstBlock "Scope1"
DstPort 3
}
}
Line {
SrcBlock "dref"
SrcPort 1
DstBlock "Mux1"
DstPort 1
}
Line {
Labels [0, 0]
SrcBlock "qref"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Sum"
SrcPort 1
Points [30, 0]
Branch {
Points [0, 255]
DstBlock "Scope1"
DstPort 4
}
Branch {
Points [10, 0]
Branch {
DstBlock "Demux1"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "dqp"
DstPort 1
}
}
}
Line {
SrcBlock "dq0_to_abc\nTransformation"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 185]
DstBlock "Scope1"
DstPort 1
}
Branch {
DstBlock "Vcontrol"
DstPort 1
}
}
Line {
SrcBlock "0 ref"
SrcPort 1
Points [25, 0; 0, -45]
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [15, 0]
Branch {
Points [0, -75]
DstBlock "dqi"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "dq0_to_abc\nTransformation"
DstPort 1
}
Branch {
Points [0, 215]
DstBlock "Scope1"
DstPort 2
}
}
}
Line {
SrcBlock "Demux1"
SrcPort 1
Points [40, 0; 0, -55]
DstBlock "Fuzzy Logic \nController d"
DstPort 1
}
Line {
SrcBlock "Fuzzy Logic \nController q"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Fuzzy Logic \nController d"
SrcPort 1
Points [15, 0; 0, 50]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 2
DstBlock "Fuzzy Logic \nController q"
DstPort 1
}
Annotation {
Name "BLOK PENGENDALI FUZZY LOGIC"
Position [495, 34]
FontSize 18
}
}
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [135, 509, 165, 541]
Orientation "left"
Floating off
Location [6, 58, 1030, 733]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveToWorkspace on
SaveName "Teg_control"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Reference
Name "Sumber 3 fasa"
Ports [0, 0, 0, 0, 0, 0, 3]
Position [135, 345, 220, 415]
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib/Electrical\nSources/Three-Phase Source"
SourceType "Three-Phase Source"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Voltage "22500"
PhaseAngle "0"
Frequency "50"
InternalConnection "Yg"
SpecifyImpedance on
Resistance "0.8929"
Inductance "16.58e-3"
ShortCircuitLevel "35000"
BaseVoltage "2e4"
XRratio "0.85"
}
Block {
BlockType Reference
Name "Transformator\nSeri"
Ports [0, 0, 0, 0, 0, 6, 6]
Position [622, 440, 738, 520]
Orientation "up"
NamePlacement "alternate"
AttributesFormatString "\\n"
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib/Elements/Three-Phase Transformer\n12 Terminals"
SourceType "Three-Phase Linear Transformer 12-Terminals"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
RatedPower "[ 15e2 50 ]"
Winding1 "[ 100 0.00001 0.0003]"
Winding2 "[ 1000 0.00001 0.0003]"
RmXm " [ 500 500 ]"
}
Block {
BlockType Reference
Name "Transformator 1"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [425, 339, 500, 421]
NamePlacement "alternate"
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