📄 fl_thesis_00_2phase.mdl
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SrcPort RConn1
Points [-65, 0]
Branch {
ConnectType "DEST_DEST"
SrcBlock "6 mH\n0.2 Ohm "
SrcPort RConn2
Points [40, 0]
}
Branch {
ConnectType "DEST_DEST"
SrcBlock "Series RLC Branch1"
SrcPort RConn1
Points [0, -55]
}
}
Line {
LineType "Connection"
SrcBlock "6 mH\n0.2 Ohm "
SrcPort RConn3
Points [55, 0]
Branch {
ConnectType "DEST_SRC"
Points [30, 0; 0, 25]
DstBlock "C "
DstPort RConn1
}
Branch {
ConnectType "DEST_DEST"
SrcBlock "Series RLC Branch2"
SrcPort RConn1
Points [0, -40]
}
}
Line {
LineType "Connection"
SrcBlock "Series RLC Branch5"
SrcPort LConn1
Points [0, 10; 15, 0]
Branch {
ConnectType "DEST_SRC"
Points [15, 0]
DstBlock "Series RLC Branch2"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "Series RLC Branch1"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "Ground1"
DstPort LConn1
}
}
Annotation {
Name "20 uF\n0.2 Ohm"
Position [262, 156]
}
}
}
Block {
BlockType Reference
Name "PWM \nIGBT Inverter"
Ports [1, 0, 0, 0, 0, 3, 2]
Position [390, 504, 455, 611]
Orientation "left"
BackgroundColor "lightBlue"
DropShadow on
AttributesFormatString "\\n"
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Arms "3"
SnubberResistance "1e4"
SnubberCapacitance "inf"
Device "IGBT / Diodes"
Ron "1e-4"
Lon "0"
ForwardVoltages "[ 2 2 ]"
ForwardVoltage ".8"
GTOparameters "[ 1e-6 ,1e-6 ]"
IGBTparameters "[ 1e-6 , 2e-6 ]"
Measurements "None"
converterType "Rectifier"
}
Block {
BlockType Reference
Name "PWM Generator"
Ports [1, 1]
Position [295, 439, 380, 481]
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib_extras/Discrete \nControl Blocks/Discrete\nPWM Generator"
SourceType "Discrete PWM Generator"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratorMode "3-arm bridge (6 pulses)"
Fc "10000"
Ts "5e-6"
Internal off
mIndex "0.4"
Freq "50"
Phase "0"
}
Block {
BlockType SubSystem
Name "Plot"
Ports []
Position [225, 155, 265, 215]
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Plot"
Location [202, 82, 1270, 754]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [315, 45, 375, 75]
VariableName "Vsource"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
Position [315, 135, 375, 165]
VariableName "Vcrload"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace2"
Position [315, 195, 375, 225]
VariableName "Vinj"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType From
Name "Vavc_1"
Position [25, 143, 60, 157]
CloseFcn "tagdialog Close"
GotoTag "V2"
TagVisibility "global"
}
Block {
BlockType From
Name "Vavc_2"
Position [25, 53, 60, 67]
CloseFcn "tagdialog Close"
GotoTag "V1"
TagVisibility "global"
}
Block {
BlockType From
Name "Vavc_4"
Position [25, 203, 60, 217]
CloseFcn "tagdialog Close"
GotoTag "V4"
TagVisibility "global"
}
Block {
BlockType Scope
Name "Vsource vs Vcritical"
Ports [2]
Position [195, 81, 225, 114]
Floating off
Location [5, 52, 1285, 769]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "V Source"
axes2 "V Critical Load"
}
YMin "-1~-1.2"
YMax "1~1.2"
SaveToWorkspace on
SaveName "Vcritical"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Line {
SrcBlock "Vavc_2"
SrcPort 1
Points [85, 0]
Branch {
DstBlock "To Workspace"
DstPort 1
}
Branch {
Points [0, 30]
DstBlock "Vsource vs Vcritical"
DstPort 1
}
}
Line {
SrcBlock "Vavc_4"
SrcPort 1
DstBlock "To Workspace2"
DstPort 1
}
Line {
SrcBlock "Vavc_1"
SrcPort 1
Points [90, 0]
Branch {
DstBlock "To Workspace1"
DstPort 1
}
Branch {
Points [0, -45]
DstBlock "Vsource vs Vcritical"
DstPort 2
}
}
}
}
Block {
BlockType SubSystem
Name "Plot Complete"
Ports []
Position [145, 155, 185, 215]
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Plot Complete"
Location [324, 82, 489, 423]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType From
Name "Iabc_2"
Position [25, 128, 60, 142]
CloseFcn "tagdialog Close"
GotoTag "I2"
TagVisibility "global"
}
Block {
BlockType Scope
Name "Scope complete"
Ports [5]
Position [85, 27, 140, 183]
Floating off
Location [5, 52, 1285, 769]
Open off
NumInputPorts "5"
List {
ListType AxesTitles
axes1 "Tegangan Sumber [pu]"
axes2 "Tegangan Beban Sensitif [pu]"
axes3 "Tegangan Injeksi"
axes4 "Arus Beban Sensitif [pu]"
axes5 "Tegangan Beban [pu]"
}
YMin "-1~-1~-40~-0.2~-1"
YMax "1~1.25~50~0.25~1"
SaveToWorkspace on
SaveName "ScopeDatapisv"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType From
Name "Vabc_1"
Position [25, 38, 60, 52]
CloseFcn "tagdialog Close"
GotoTag "V1"
TagVisibility "global"
}
Block {
BlockType From
Name "Vabc_22"
Position [25, 68, 60, 82]
CloseFcn "tagdialog Close"
GotoTag "V2"
TagVisibility "global"
}
Block {
BlockType From
Name "Vabc_3"
Position [25, 158, 60, 172]
CloseFcn "tagdialog Close"
GotoTag "V3"
TagVisibility "global"
}
Block {
BlockType From
Name "Vavc_4"
Position [25, 98, 60, 112]
CloseFcn "tagdialog Close"
GotoTag "V4"
TagVisibility "global"
}
Line {
SrcBlock "Vabc_1"
SrcPort 1
DstBlock "Scope complete"
DstPort 1
}
Line {
SrcBlock "Vabc_22"
SrcPort 1
DstBlock "Scope complete"
DstPort 2
}
Line {
SrcBlock "Iabc_2"
SrcPort 1
DstBlock "Scope complete"
DstPort 4
}
Line {
SrcBlock "Vabc_3"
SrcPort 1
DstBlock "Scope complete"
DstPort 5
}
Line {
SrcBlock "Vavc_4"
SrcPort 1
DstBlock "Scope complete"
DstPort 3
}
}
}
Block {
BlockType SubSystem
Name "Regulator Tegangan"
Ports [1, 1]
Position [185, 442, 250, 478]
BackgroundColor "lightBlue"
TreatAsAtomicUnit on
MinAlgLoopOccurrences on
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Regulator Tegangan"
Location [284, 86, 1270, 749]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 74
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "125"
Block {
BlockType Inport
Name "V2"
Position [100, 333, 130, 347]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Constant
Name "0 ref"
Position [495, 225, 520, 245]
BackgroundColor "lightBlue"
Value "0"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Demux
Name "Demux1"
Ports [1, 2]
Position [375, 136, 380, 174]
BackgroundColor "black"
ShowName off
Outputs "2"
}
Block {
BlockType Reference
Name "Discrete\nVirtual PLL"
Ports [0, 3]
Position [20, 398, 75, 452]
DialogController "POWERSYS.PowerSysDialog"
SourceBlock "powerlib_extras/Discrete \nControl Blocks/Discrete\nVirtual PLL"
SourceType "Discrete Virtual PLL"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Freq "50"
Phase "0"
Ts "1e-6"
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController d"
Ports [1, 1]
Position [465, 66, 525, 114]
BackgroundColor "lightBlue"
SourceBlock "fuzblock/Fuzzy Logic \nController"
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