tc.inc

LPC based lcd interface

/*
-----------------------------------------------------------------------------
-      ATMEL Microcontroller Software Support  -   ROUSSET -
-----------------------------------------------------------------------------
 The software is delivered "AS IS" without warranty or condition of any
 kind, either express, implied or statutory. This includes without
 limitation any warranty or condition with respect to merchantability or
 fitness for any particular purpose, or against the infringements of
 intellectual property rights of others.
-----------------------------------------------------------------------------
- File Name            : tc.inc
- Object               : Timer Counter Definition File.
- Translator           : ARM Software Development Toolkit V2.11a
-
- 1.0 19/08/97 JCZ     : Creation
- 1.1 16/06/98 JCZ     : Update register names same as header file
- 2.0 21/10/98 JCZ     : Clean up.
-----------------------------------------------------------------------------
*/
/*
------------------------
 Timer Counter Structure
------------------------
*/
.equ TC_CCR,0x00       /* Channel Control Register */
.equ TC_CMR,0x04       /* Channel Mode Register */

.equ TC_CV,0x10       /* Counter Value */
.equ TC_RA,0x14       /* Register A */
.equ TC_RB,0x18       /* Register B */
.equ TC_RC,0x1c       /* Register C */
.equ TC_SR,0x20       /* Status Register */
.equ TC_IER,0x24      /* Interrupt Enable Register */
.equ TC_IDR,0x28       /* Interrupt Disable Register */
.equ TC_IMR,0x2c       /* Interrupt Mask Register */

.equ TC_SIZE,0x30

/*
------------------------------
 Timer Counter Block Structure
------------------------------
*/
.equ TC0,TC_SIZE
.equ TC1,TC_SIZE
.equ TC2,TC_SIZE
.equ TC_BCR,4
.equ TC_BMR,4
/*
-------------------------------------------------
- Timer Counter Control Register Bits Definition
-------------------------------------------------
*/
.equ CLKEN,(1<<0)
.equ CLKDIS,(1<<1)
.equ SWTRG,(1<<2)
/*
----------------------------------------------
- Timer Counter Mode Register Bits Definition
----------------------------------------------
*/
/*- Clock Selection */
.equ TCCLKS,(0x7<<0)

/*- Clock Inversion */
.equ CLKI,0x08

/*- Burst Signal Selection */
.equ BURST,(0x3<<4)

/*- Capture Mode : Counter Clock Stopped with RB Loading */
.equ LDBSTOP,0x40

/*- Waveform Mode : Counter Clock Stopped with RC Compare */
.equ CPCSTOP,0x40

/*- Capture Mode : Counter Clock Disabled with RB Loading */
.equ LDBDIS,0x80

/*- Waveform Mode : Counter Clock Disabled with RC Compare */
.equ CPCDIS,0x80

/*- Capture Mode : External Trigger Edge Selection */
.equ ETRGEDG,(0x3<<8)

/*- Waveform Mode : External Event Edge Selection */
.equ EEVTEDG,(0x3<<8)

/*- Capture Mode : TIOA or TIOB External Trigger Selection */
.equ ABETRG,0x400

/*- Waveform Mode : External Event Selection */
.equ EEVT,(0x3<<10)

/*- Waveform Mode : Enable Trigger on External Event */
.equ ENETRG,0x1000

/*- RC Compare Enable Trigger Enable */
.equ CPCTRG,0x4000

/*- Mode Selection */
.equ WAVE,0x8000

/*- Capture Mode : RA Loading Selection */
.equ LDRA,(0x3<<16)

/*- Waveform Mode : RA Compare Effect on TIOA */
.equ ACPA,(0x3<<16)

/*- Capture Mode : RB Loading Selection */
.equ LDRB,(0x3<<18)

/*- Waveform Mode : RC Compare Effect on TIOA */
.equ ACPC,(0x3<<18)

/*- Waveform Mode : External Event Effect on TIOA */
.equ AEEVT,(0x3<<20)

/*- Waveform Mode : Software Trigger Effect on TIOA */
.equ ASWTRG,(0x3<<22)

/*- Waveform Mode : RB Compare Effect on TIOB */
.equ BCPB,(0x3<<24)

/*- Waveform Mode : RC Compare Effect on TIOB*/
.equ BCPC,(0x3<<26)

/*- Waveform Mode : External Event Effect on TIOB */
.equ BEEVT,(0x3<<28)

/*- Waveform Mode : Software Trigger Effect on TIOB */
.equ BSWTRG,(0x3<<30)
/*
------------------------------------------------
- Timer Counter Status Register Bits Definition
------------------------------------------------
*/
/*- Counter Overflow Status */
.equ COVFS,0x01
/*- Load Overrun Status */
.equ LOVRS,0x02
/*- RA Compare Status */
.equ CPAS,0x04
/*- RB Compare Status */
.equ CPBS,0x08
/*- RC Compare Status */
.equ CPCS,0x10
/*- RA Loading Status */
.equ LDRAS,0x20
/*- RB Loading Status */
.equ LDRBS,0x40
/*- External Trigger Status */
.equ ETRGS,0x80
/*- Clock Status */
.equ CLKSTA,0x10000
/*- TIOA Mirror */
.equ MTIOA,0x20000
/*- TIOB Status */
.equ MTIOB,0x40000
/*
-------------------------------------------------------
- Timer Counter Block Control Register Bits Definition
-------------------------------------------------------
*/
/*- Synchronisation Trigger */
.equ TCSYNC,0x1
/*
----------------------------------------------------
- Timer Counter Block Mode Register Bits Definition
----------------------------------------------------
*/
/*- External Clock Signal 0 Selection */
.equ TC0XC0S,(0x3<<0)

/*- External Clock Signal 1 Selection */
.equ TC1XC1S,(0x3<<2)

/*- External Clock Signal 2 Selection */
.equ TC2XC2S,(0x3<<4)
/*
--------------------------------
- Device Dependancies Definition
--------------------------------
*/
    .IFDEF AT91M40400
.equ NB_TC_BLOCK,1
.equ TCB_BASE,0xFFFE0000
    .ENDIF