usart.inc

LPC based lcd interface

/*
-----------------------------------------------------------------------------
-      ATMEL Microcontroller Software Support  -   ROUSSET -
-----------------------------------------------------------------------------
 The software is delivered "AS IS" without warranty or condition of any
 kind, either express, implied or statutory. This includes without
 limitation any warranty or condition with respect to merchantability or
 fitness for any particular purpose, or against the infringements of
 intellectual property rights of others.
-----------------------------------------------------------------------------
- File Name            : usart.inc
- Object               : USART Definition File.
- Translator           : ARM Software Development Toolkit V2.11a
-
- 1.0 10/03/98 JCZ     : Creation
- 2.0 21/10/98 JCZ     : Clean up.
-----------------------------------------------------------------------------
*/
/*
----------------
 USART Structure
----------------
*/
.equ	US_CR,0x00       /* Control Register */
.equ	US_MR,0x04       /* Mode Register */
.equ	US_IER,0x08       /* Interrupt Enable Register */
.equ	US_IDR,0x0c       /* Interrupt Disable Register */
.equ	US_IMR,0x10       /* Interrupt Mask Register */
.equ	US_CSR,0x14       /* Status Register */
.equ	US_RHR,0x18       /* Receive Holding Register */
.equ	US_THR,0x1c       /* Transmit Holding Register */
.equ	US_BRD,0x20       /* Baud Rate Generator Register */
.equ	US_RTOR,0x24       /* Receive Time Out Register */
.equ	US_TTGR,0x28       /* Transmit Time Guard Register */

.equ	US_RPR,0x30       /* receive Pointer Register */
.equ	US_RCR,0x34       /* Receive Counter Register */
.equ	US_TPR,0x38       /* Transmit Pointer Register */
.equ	US_TCR,0x3c       /* Transmit Counter Register */

/*
-------------------
- Control Register
-------------------
*/
/*- Reset Receiver */
.equ	RSTRX,0x04
/*- Reset Transmitter */
.equ	RSTTX,0x08
/*- Receiver Enable */
.equ	RXEN,0x10
/*- Receiver Disable */
.equ	RXDIS,0x20
/*- Transmitter Enable */
.equ	TXEN,0x40
/*- Transmitter Disable */
.equ	TXDIS,0x80
/*- Reset Status Bits */
.equ	RSTSTA,0x100
/*- Start Break */
.equ	STTBRK,0x200
/*- Stop Break */
.equ	STPBRK,0x400
/*- Start Timeout */
.equ	STTTO,0x800
/*- Send Address */
.equ	SENDA,0x1000
/*- Force Load */
.equ	FORCEL,0x10000

/*
;----------------
;- Mode Register
;----------------
*/
/*- Clock Selection */
.equ	CLKS,0x30

/*- Byte Length */
.equ	CHRL,0xC0

/*- Synchronous Mode Enable */
.equ	SYNC,0x100

/*- Parity Mode */
.equ	PAR,(0x7<<9)

/*- Stop Bit Number */
.equ	NBSTOP,(0x3<<12)

/*- Channel Mode */
.equ	CHMODE,(0x3<<14)

/*- 9 Bit Mode */
.equ	MODE9,0x20000

/*- Baud Rate Output Enable */
.equ	CLKO,0x40000

/*
;--------------------------
;- Channel Status Register
;--------------------------
*/
/*- Receiver Ready */
.equ	RXRDY,0x01

/*- Transmitter Ready */
.equ	TXRDY,0x02

/*- Receiver Break */
.equ	RXBRK,0x04

/*- End of Receiver PDC Transfer */
.equ	ENDRX,0x08

/*- End of Transmitter PDC Transfer */
.equ	ENDTX,0x10

/*- Overrun Error */
.equ	OVRE,0x20

/*- Framing Error */
.equ	FRAME,0x40

/*- Parity Error */
.equ	PARE,0x80

/*- Receiver Timeout */
.equ	TIMEOUT,0x100

/*- Transmitter Empty */
.equ	TXEMPTY,0x200

/*- USART Handler Table Structure */
.equ	ErrorMask,0x00
.equ	ErrorHandler,0x04
.equ	RxMask,0x08
.equ	RxHandler,0x0c
.equ	TxMask,0x10
.equ	TxHandler,0x14

.equ	SIZE_USART_HANDLER_TABLE,0
/*
;--------------------------------
;- Device Dependancies Definition
;--------------------------------
*/
    .ifdef AT91M40400

.equ	NB_USART,2
.equ	USART0_BASE,0xFFFD0000
.equ	USART1_BASE,0xFFFCC000

    .ENDIF