📄 in_reset.s
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/*
------------------------------------------------------------------------------
- ATMEL Microcontroller Software Support - ROUSSET -
------------------------------------------------------------------------------
The software is delivered "AS IS" without warranty or condition of any
kind, either express, implied or statutory. This includes without
limitation any warranty or condition with respect to merchantability or
fitness for any particular purpose, or against the infringements of
intellectual property rights of others.
-----------------------------------------------------------------------------
- File source : in_reset.s
- Object : Boot of AT91EB01/DB01
- Translator : ARM Software Development Toolkit V2.11a
-
- Exported Resources : __main - InitResetStacks
- Imported Resources : MainApplication - InitTableEBI - InitTableStack
-
- 1.0 15/09/98 JLV : Creation
- 2.0 21/10/98 JCZ : Clean up.
- 2.1 16/03/99 JCZ : SDT V2.5
- : Remove warning concerning CPSR field specifier.
- : Reserve stack space on top of memory for ICE Debug.
------------------------------------------------------------------------------
*/
/* AREA IN_RESET, CODE, READONLY, INTERWORK
*/
/* -------------------------- List of Included Files --------------------------- */
.INCLUDE "../../Include/arm.inc"
.INCLUDE "../../Include/int_mem.inc"
.INCLUDE "../../Include/aic.inc"
.IFDEF AT91DB01
.INCLUDE "../../Include/pio.inc"
.INCLUDE "../../Include/db01.inc"
.ENDIF
/* ------------------------ List of constants and types ------------------------ */
/* None */
/* ------------------------ List of Imported resources ------------------------- */
.extern InitMainSram
.extern InitTableStack
.IFDEF AT91_DEBUG_NONE
.extern InitTableEBI
.extern MainApplication
.extern |Image$$RO$$Limit| /* End of ROM code (=start of ROM data) */
.extern |Image$$RW$$Base| /* Base of RAM to initialise */
.extern |Image$$ZI$$Base| /* Base and limit of area */
.extern |Image$$ZI$$Limit| /* to zero initialise */
.ENDIF
/* ------------------------ List of Internal resources ------------------------- */
/* None */
/* ------------------------ List of Exported resources ------------------------- */
.IFDEF AT91_DEBUG_NONE
/*- Define the entry point */
/* ENTRY*/
/*
------------------------------------------------------------------------------
- Function : boot
- Treatments : AT91 boot code
- Input Parameters : None
- Output Parameters : None
- Registers lost : None
- Called Functions : MainApplication
- Called Macros : None
------------------------------------------------------------------------------
*/
/*- Define "__main" to ensure that C runtime system is not linked */
.global __main
__main:
.long InitReset /* reset */
undefvec:
.long undefvec /* Undef */
swivec:
.long swivec /* SW */
pabtvec:
.long pabtvec /* P abt */
dabtvec:
.long dabtvec /* D abt */
rsvdvec:
.long rsvdvec /* reserved */
irqvec:
ldr pc, [pc,#-0xF20] /* IRQ : read the AIC */
fiqvec:
ldr pc, [pc,#-0xF20] /* FIQ : read the AIC */
InitReset:
/*
- | Initialise the Memory Controller
- | ---------------------------------
- | Copy the Image of the Memory Controller
*/
ldr r10, PtInitTableEBI /* get the address of the chip select register image */
/*- | If pc > 0x100000 */
movs r0, pc, LSR #20
/*- | | Mask the 12 highest bits of the address */
moveq r10, r10, LSL #12
moveq r10, r10, LSR #12
/*- | EndIf */
/*- | Load the address where to jump */
ldr r12, PtInitRemap /* get the real jump address ( after remap ) */
/*- | Copy Chip Select Register Image to Memory Controller and command remap */
ldmia r10!, {r0-r9,r11} /* load the complete image and the EBI base */
stmia r11!, {r0-r9} /* store the complete image with the remap command */
/*- | Jump to ROM at its new address */
mov pc, r12 /* jump and break the pipeline */
PtInitTableEBI:
.long InitTableEBI /* Table for EBI initialization */
PtInitRemap:
.long InitRemap /* address where to jump after REMAP */
PtInitVector:
.long __main /* Table for vector initialization */
InitRemap:
/*
- | Setup Exception Vectors
- | -----------------------
- | Copy the hard exception vectors
*/
mov r8, #0 /* @ of the hard vector */
ldr r9, PtInitVector /* @ where to read values */
ldmia r9!, {r0-r7} /* read the vectors */
stmia r8!, {r0-r7} /* store them */
/*- | Set up the SVC mode and stack pointer on the top of the internal RAM */
mov r0, #ARM_MODE_SVC | I_BIT | F_BIT /* No interrupts */
msr cpsr_c, r0
ldr r13, =RAM_LIMIT
/*- | Initialize the Stacks */
bl InitResetStacks
/*- | Initialise memory required by C code */
ldr r0, =|Image$$RO$$Limit| /* Get pointer to ROM data */
ldr r1, =|Image$$RW$$Base| /* and RAM copy */
ldr r3, =|Image$$ZI$$Base| /* Zero init base => top of initialised data */
cmp r0, r1 /* Check that they are different */
beq NoRW
LoopRw: cmp r1, r3 /* Copy init data */
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRw
NoRW: ldr r1, =|Image$$ZI$$Limit| /* Top of zero init segment */
mov r2, #0
LoopZI: cmp r3, r1 /* Zero init */
strcc r2, [r3], #4
bcc LoopZI
/*- | Branch on C code Main function */
ldr r0, =MainApplication
mov lr, pc
bx r0
/*- | Loop for ever */
InitEnd:
b InitEnd
.ENDIF
.IFDEF AT91_DEBUG_ICE
irqvec:
ldr pc, [pc,#-0xF20] /* IRQ : read the AIC */
fiqvec:
ldr pc, [pc,#-0xF20] /* FIQ : read the AIC */
.ENDIF
/*
------------------------------------------------------------------------------
- Function : InitResetStacks
- Treatments : AT91 boot code
- Must be call in Supervisor mode
- Input Parameters : None
- Output Parameters :
- <AdFiq> = address of FIQ treatment which initialize the stack
- Registers lost : None
- Called Functions : None
- Called Macros : None
------------------------------------------------------------------------------
*/
.global InitResetStacks
InitResetStacks:
ldr r1, =AIC_BASE
.IFDEF AT91_DEBUG_ANGEL
/*- Disable all interrupt unless USART used by Angel */
mvn r0, #(1<<US0IRQ)
.ELSE
/*- Disable all interrupt */
mvn r0, #0
.ENDIF
str r0, [r1, #AIC_IDCR]
/*- Perform 8 End Of Interrupt Command to make sure AIC will not lock out nIRQ */
mov r0, #8
LoopAic:
str r1, [r1, #AIC_EOICR]
subs r0, r0, #1
bhi LoopAic
.IFDEF AT91_DEBUG_ICE
/*- | -- Set IRQ and FIQ interrupt vectors */
adr r0, irqvec /* @ where to read values */
ldmia r0!, {r1-r2} /* read the vectors */
mov r0, #(6*4) /* @ of the interrupt vector */
stmia r0!, {r1-r2} /* store them */
.ENDIF
.IFDEF AT91EB01
/*
- | -- Get the top of the SRAM
- | top <- InitMainSram()
*/
stmfd r13!, {lr}
ldr r0, =InitMainSram
mov lr, pc
bx r0
ldmfd r13!, {lr}
.ENDIF
.IFDEF AT91DB01
/*- | -- Get the top of the SSRAM
- | top <- SSRAM_BASE
*/
ldr r0, =SSRAM_LIMIT
.ENDIF
/*- | -- Save current CPSR and work registers */
mrs r12, cpsr
/*- | Get the size of the stacks */
ldr r2, =InitTableStack
/*- | Reserve debugger stack size */
ldr r3, [r2, #0]
sub r0, r0, r3
.IFNDEF AT91_DEBUG_ANGEL
/*- | If (FIQ size defined) */
ldr r3, [r2, #0]
teq r3, #0
/*- | Then */
beq InitFiqEnd
/*- | | -- Set up Fast Interrupt mode and set FIQ stack */
mov r1, #ARM_MODE_FIQ | I_BIT | F_BIT
msr cpsr_c, r1
/*- | | FIQ_r13 <- top */
mov r13, r0
/*- | | top <- top - size_FIQ */
sub r0, r0, r3
/*- | Endif */
InitFiqEnd:
/*- | If (IRQ size defined) */
ldr r3, [r2, #4]
teq r3, #0
/*- | Then */
beq InitIrqEnd
/*- | | -- Set up Interrupt mode and set IRQ stack */
mov r1, #ARM_MODE_IRQ | I_BIT | F_BIT
msr cpsr_c, r1
/*- | | IRQ_r13 <- top */
mov r13, r0
/*- | | top <- top - size_IRQ */
sub r0, r0, r3
/*- | Endif */
InitIrqEnd:
.IFNDEF AT91_DEBUG_ICE
/*- | If (SVC size defined) */
ldr r3, [r2, #8]
teq r3, #0
/*- | Then */
beq InitSvcEnd
/*- | | -- Set up Supervisor mode and set SVC stack */
mov r1, #ARM_MODE_SVC | I_BIT | F_BIT
msr cpsr_c, r1
/*- | | SVC_r13 <- top */
mov r13, r0
/*- | | top <- top - size_SVC */
sub r0, r0, r3
/*- | Endif */
InitSvcEnd:
.ENDIF
.ENDIF
/*- | If (ABORT size defined) */
ldr r3, [r2, #12]
teq r3, #0
/*- | Then */
beq InitAbortEnd
/*- | | -- Set up Abort mode and set ABORT stack */
mov r1, #ARM_MODE_ABORT | I_BIT | F_BIT
msr cpsr_c, r1
/*- | | Abort_r13 <- top */
mov r13, r0
/*- | | top <- top - size_ABORT */
sub r0, r0, r3
/*- | Endif */
InitAbortEnd:
/*- | If (UNDEF size defined) */
ldr r3, [r2, #16]
teq r3, #0
/*- | Then */
beq InitUndefEnd
/*- | | -- Set up Undefined mode and set UNDEF stack */
mov r1, #ARM_MODE_UNDEF | I_BIT | F_BIT
msr cpsr_c, r1
/*- | | UNDEF_r13 <- top */
mov r13, r0
/*- | | top <- top - size_UNDEF */
sub r0, r0, r3
/*- | Endif */
InitUndefEnd:
/*- | -- Set up USER/SYStem mode and set USER/SYStem stack */
mov r1, #ARM_MODE_SYS | I_BIT | F_BIT
msr cpsr_c, r1
/*- | r13 <- top */
mov r13, r0
/*- | -- Restore current CPSR enabling interrupt and fast interrupt */
bic r12, r12, #I_BIT | F_BIT
msr cpsr, r12
/*- | return */
bx lr
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