blank_gen.v.bak

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module blank_gen(
	rst,
	datack,
	hsync,
	vsync,
	blank_rev,
	vsync_rev,
	vsout
                );
input	rst,datack,hsync,vsync;

output	blank_rev;
output  vsync_rev;
output	vsout;

reg	blank_rev_svga;
wire	blank_rev;
reg	vsync_rev;
reg	vsout;

reg	[11:0]	hcnt_h,vcnt_h,hcnt_l,vcnt_l;
reg	hsync_reg1,hsync_reg2,vsync_reg1,vsync_reg2;

always @ (posedge datack) begin
	hsync_reg1 <= hsync;
	hsync_reg2 <= hsync_reg1;
	vsync_reg1 <= vsync;
	vsync_reg2 <= vsync_reg1;
	end
	
always @ (posedge datack or negedge rst)
if(!rst)
	vcnt_h <= 0;
else if(vsync_reg1) begin
	if(hsync_reg1 & !hsync_reg2)
		vcnt_h <= vcnt_h + 1;
	end
else 
	vcnt_h <= 0;

always @ (posedge datack or negedge rst)
if(!rst)
	vcnt_l <= 0;
else if(!vsync_reg1) begin
	if(hsync_reg1 & !hsync_reg2)
		vcnt_l <= vcnt_l + 1;
	end
else 
	vcnt_l <= 0;

always @ (posedge datack or negedge rst)
if(!rst)
	vsync_rev <= 0;
else if((vcnt_l<'d2 && !vsync_reg1) || (vcnt_h>'d0))
	vsync_rev <= 1;
else
	vsync_rev <= 0;

always @ (posedge datack or negedge rst)
if(!rst)
	vsout <= 0;
else if((vcnt_l<'d1 && !vsync_reg1) || (vcnt_h>'d1))
	vsout <= 1;
else
	vsout <= 0;
			
always @ (posedge datack or negedge rst)
if(!rst)
	hcnt_h <= 0;
else if(hsync_reg1)
	hcnt_h <= hcnt_h + 1;
else 
	hcnt_h <= 0;

always @ (posedge datack or negedge rst)
if(!rst)
	hcnt_l <= 'd0;
else if(!hsync_reg1)
	hcnt_l <= hcnt_l + 1;
else 
	hcnt_l <= 'd0;	
/*******************************************************/
/***********Generate Blanks for SVGA 800*600************/
/*******************************************************/
always @ (posedge datack or negedge rst)
if(!rst)
	blank_rev_svga<=0;
else begin//91 897
	if(((hcnt_h >=40) || ((!hsync_reg1)&& (hcnt_l < 'd112))) &&  vsync_rev)//)// (vcnt_h > 0)&& (vcnt_h < 288) 
		blank_rev_svga<=1;
	else
		blank_rev_svga<=0;
end

assign	blank_rev =  blank_rev_svga ;





endmodule