arbiter.v.bak

来自「详细介绍SDRAM原理的中文电子书籍」· BAK 代码 · 共 118 行

module arbiter(
	rst,
	
	clk_dsp,
	db_dsp,
	wr_dsp,
	rd_dsp,
	
	ce_dsp,
	oe_dsp,
	
	ram_rdb,
	ram_rab,
	s_raw_req,
	s_raw_ack,
	
	ram_wdb,
	ram_wab,
	ram_wen,
	r_req,
	r_ack	
	);
	
input	rst;
input	clk_dsp;
inout	[15:0]	db_dsp;
input	wr_dsp;
input	rd_dsp;

input	[7:0]	ram_rdb;

output	[8:0]	ram_rab;
output	r_req;
input	r_ack;
	
input	oe_dsp,ce_dsp;
output	[1:0]	ram_wdb;
output	[10:0]	ram_wab;
output	ram_wen;
output	s_raw_req;
input	s_raw_ack;

//***********************data from the dsp***************************//
//*********************receive the mask picture**********************//	
reg	[9:0]	ram_wab_reg;
reg	ram_wab_hbit;

always @ (posedge clk_dsp or negedge rst)
if(!rst)
	ram_wab_reg <= 0;
else if((ram_wen) & (!ce_dsp)) begin
	if(ram_wab_reg == 'd719)
		ram_wab_reg <= 0;
	else
		ram_wab_reg <= ram_wab_reg + 1;
	end
	
always @ (posedge clk_dsp or negedge rst)
if(!rst)
	ram_wab_hbit <= 0;
else if(ram_wab_reg == 'd719 && ram_wen)
	ram_wab_hbit <= ~ram_wab_hbit;

wire	[10:0] ram_wab = {ram_wab_hbit,ram_wab_reg};		

reg	[1:0]	ram_wdb;
always @ (posedge clk_dsp or negedge rst)
if(!rst)
	ram_wdb <= 0;
else
	ram_wdb <= {db_dsp[1:0]};

reg	ram_wen;
always @ (posedge clk_dsp)
ram_wen <= ~wr_dsp;

reg	r_req;
always @ (posedge clk_dsp or negedge rst)
if(!rst)
	r_req <= 0;
else if(ram_wab_reg=='d719)
	r_req <= 1;
else if(r_ack)
	r_req <= 0;
		
//***********************data to the dsp****************************//
//**********************send the raw picture**********************//
reg	rd_cnl;
always @ (posedge clk_dsp)
rd_cnl <= rd_dsp;
	
reg	[8:0]	ram_rab;
always @ (posedge clk_dsp or negedge rst)
if(!rst)
	ram_rab <= 0;
else if((!rd_dsp & rd_cnl)&(!ce_dsp)&(!oe_dsp)) begin
	if(ram_rab == 'd359)
		ram_rab <= 'd0;
	else
		ram_rab <= ram_rab + 1;
	end
	
reg	[7:0]	db_dsp_reg;		
always @ (posedge clk_dsp)
db_dsp_reg <= ram_rdb;

reg	s_raw_req;
always @ (posedge clk_dsp or negedge rst)
if(!rst)
	s_raw_req <= 0;
else if(ram_rab == 'd358)
	s_raw_req <= 1;
else //if(s_raw_ack)
	s_raw_req <= 0;
	
wire	[15:0]	db_dsp = (oe_dsp|ce_dsp)?16'hz:{8'd0,db_dsp_reg};
endmodule