mesure_card_top.v.bak

详细介绍SDRAM原理的中文电子书籍

module mesure_card_top(      
	clkin  ,             
	rst  ,               
	H_sig,               
	V_sig,               
	odd_even_sig,        
	qd   ,               
	qck  ,               
   
	pixel_video,         
	                     
	hsout_vga,           
	vsout_vga,           
	pixel_R,             
	pixel_G,             
	pixel_B,             
	blankout_vga,        
	                     
	                     
	dq    ,              
	sa    ,              
	ba    ,              
	cke   ,              
	cs_n  ,              
	ras_n ,              
	cas_n ,              
	we_n  ,              
	sdram_clk,           
	dqm,                 
	mode_vga,            
	                     
	dq_dsp    ,          
	sa_dsp    ,          
	ba_dsp    ,          
	cke_dsp   ,          
	cs_n_dsp  ,          
	ras_n_dsp ,          
	cas_n_dsp ,          
	we_n_dsp  ,          
	clk40m    ,          
	                     
	clk_dsp,             
	db_dsp,              
	wr_dsp,              
	rd_dsp,              
	oe_dsp,
	ce_dsp,                    
	raw_demand,    	 
        raw_send_int,        
        mask_demand,         
        mask_receive_int        
   
);
input	mode_vga;
input	clkin;
input	rst  ;
input	H_sig;
input	V_sig;
input	odd_even_sig;
input	[7:0]	qd   ;
input	qck  ;
input	clk40m;

inout	[31:0]	dq     ;
output	[10:0]	sa     ;
output	[1:0]	ba     ;
output	cke    ;
output	cs_n   ;
output	ras_n  ;
output	cas_n  ;
output	we_n   ;
output	sdram_clk;
output	[3:0]	dqm;

inout	[15:0]	dq_dsp     ;
output	[10:0]	sa_dsp     ;
output	[1:0]	ba_dsp     ;
output	cke_dsp    ;
output	cs_n_dsp   ;
output	ras_n_dsp  ;
output	cas_n_dsp  ;
output	we_n_dsp   ;

output	[7:0]	pixel_video;

output	hsout_vga;
output	vsout_vga;
output	[7:0]	pixel_R;
output	[7:0]	pixel_G;
output	[7:0]	pixel_B;
output	blankout_vga;

input	clk_dsp;
inout	[15:0]	db_dsp;
input	wr_dsp;
input	rd_dsp;

input	raw_demand;
output	raw_send_int;
input	mask_demand;
output	mask_receive_int;
input	oe_dsp;
input	ce_dsp;                 
wire [15:0]  s_fifo_wdb ;
wire [8:0 ]  s_fifo_wab ;
wire         s_fifo_wck ;
wire         s_fifo_wen ;
wire         s_req      ;
wire         s_ack      ;                    
                   
wire         start_read ;                        
wire         s_fifo_rst ;
wire         vsout      ;
wire         test_pin   ;

wire        s_fifo_rck;
wire        s_fifo_ren;
wire [9:0]  s_fifo_rab;
wire        data_valid;  


assign      dqm = 4'd0;
	
assign    clk = clkin;   

wire	[7:0]	qd_i;
wire	qck_i;
wire	H_sig_i;
wire	V_sig_i;
wire	odd_even_sig_i;

image_NTSC source(	
	.rst(rst),
	.clk27m(qck),
	.qd(qd_i),
	.hsync(H_sig_i),
	.vsync(V_sig_i),
	.odd_even_out(odd_even_sig_i)
	);
		
wire	blank,vsync_rev;
wire	vsout_video;
wire	blank_video_send; 
blank_gen blank_gen0(
	.rst(rst),
	.datack(qck),
	.hsync(H_sig),
	.vsync(V_sig),
	.blank_rev(blank),
	.vsync_rev(vsync_rev),
	.vsout(vsout_video),
	.blank_video_send(blank_video_send)
        );			
wire	[7:0]	r_ram_wdb;
wire	[9:0]	r_ram_wab;
wire	[7:0]	qd,r_ram_wdb_test;
wire	qck;
wire	H_sig;
wire	V_sig;
wire	odd_even_sig;
       
wire	r_req,r_req_dsp;
wire	[8:0]	 r_ram_wab_raw;
wire	r_ack_dsp,r_ack_video;
wire	r_busy;
   
receiver receiver1( 
	.rst      (rst)  ,	
	.H_sig    (H_sig)  ,
	.V_sig    (vsync_rev)  ,//V_sig
	.qd       (qd)  ,
	.clk      (qck)  ,
	.qfv      (blank)  ,
	.odd_even_sig(odd_even_sig),
	          
	.r_ram_wdb(r_ram_wdb)  ,
	.r_ram_wdb_test(r_ram_wdb_test),
	.r_ram_wab(r_ram_wab)  ,
	.r_ram_wab_raw(r_ram_wab_raw),         
	.r_req    (r_req    ),
	.r_ack_video(r_ack_video),
	.r_busy(r_busy),
	
	.r_req_dsp(r_req_raw),
	.r_ack_dsp(r_ack_raw),
	
	.start_read(start_read),
	.mode_vga(mode_vga)  	  
		);
		
wire	[7:0]	r_ram_rab;
wire	[31:0]	r_ram_rdb;
		
ram1k_8to256_32 ram_r0( 
	.data     (r_ram_wdb)  ,//r_ram_wdb_test //Changed by Yaoyuan 2005.07.24
	.wren     (1'b1     )  ,
	.wraddress(r_ram_wab)  ,
	.rdaddress(r_ram_rab)  ,
	.wrclock  (qck)  ,
	.rdclock  (clk)  ,
	.q        (r_ram_rdb)
	);  

wire	[15:0]	r_ram_rdb_raw  ;    
wire	[7:0]	r_ram_rab_raw  ; 
	
ram512_8to256_16 ram_r1( 
	.data(r_ram_wdb)  ,//r_ram_wdb_test //Changed by Yaoyuan 2005.07.24
	.wren(1'b1     )  ,
	.wraddress(r_ram_wab_raw)  ,
	.rdaddress(r_ram_rab_raw)  ,
	.wrclock(qck)  ,
	.rdclock(clk)  ,
	.q(r_ram_rdb_raw)
	);   	      	            
wire	start_send;
wire	[8:0]	s_ram_wab;
wire	[31:0]	s_ram_wdb;
wire	[7:0]	s_ram_wab_video;
wire	[2:0]	cmd        ;
wire	cmdack     ;
wire	[20:0]	addr       ;
wire	[31:0]	datain     ;
wire	[31:0]	dataout    ;
wire	V_sig_vga;     
wire	s_ack_raw;
wire	s_req_raw_vga,s_req_raw_video;
assign	s_req = mode_vga ? s_req_raw_vga : s_req_raw_video;    
datacnl  datacnl1( 
	.clk       (clk)   ,
	.rst       (rst)   ,
	              
	.r_ram_rdb (r_ram_rdb),
	.r_ram_rab (r_ram_rab),
	.r_req_in  (r_req    ),
	.r_ack(r_ack_video),
	.r_busy(r_busy),
                    
	.s_ram_wdb(s_ram_wdb),
	.s_ram_wab(s_ram_wab),
	.s_ram_wab_video(s_ram_wab_video),
	.s_ram_wen(s_ram_wen),
	.s_req_in (s_req),
	.s_ack(s_ack),
	           
	.cmd      (cmd      ),
	.cmdack   (cmdack   ),
	.addr     (addr     ),
	.datain   (datain   ),
	.dataout  (dataout  ),
	                              
	.start_read(start_read),
	.mode_vga_in(mode_vga),
	
	.start_send(start_send),
	.vsync     (vsync_rev),
	.vsync_vga(!V_sig_vga)                
                );  
                
wire [10:0]  sa   ; 
wire [1:0]   ba   ; 
wire         cs_n ;
wire         cke  ;
wire         ras_n;
wire         cas_n;
wire         we_n ;
wire [31:0]  dq   ;  
 
sdr_sdram sdr_sdram1(
        .CLK    (clk),
        .RESET_N(rst),
        .ADDR   (addr),
        .CMD    (cmd),
        .CMDACK (cmdack),
        .DATAIN (datain),    
        .DATAOUT(dataout),

        .SA     (sa),
        .BA     (ba),
        .CS_N   (cs_n),
        .CKE    (cke),
        .RAS_N  (ras_n),
        .CAS_N  (cas_n),
        .WE_N   (we_n),
        .DQ     (dq)
        );
wire	[7:0]	s_ram_rdb_raw_video;    
wire	[9:0]	s_ram_rab_raw_video;

ram256_32to1k_8 ram_s0( 
	.data     (s_ram_wdb),
	.wren     (s_ram_wen),
	.wraddress(s_ram_wab),
	.rdaddress(s_ram_rab_raw_video),
	.wrclock  (clk),
	.rdclock  (qck),
	.q        (s_ram_rdb_raw_video)
	);  

wire	[31:0]	s_ram_rdb_raw_vga;    
wire	[8:0]	s_ram_rab_raw_vga; 
	
ram512_32 ram_s1( 
	.data     (s_ram_wdb),
	.wren     (s_ram_wen),
	.wraddress(s_ram_wab),
	.rdaddress(s_ram_rab_raw_vga),
	.wrclock  (clk),
	.rdclock  (clk40m),
	.q        (s_ram_rdb_raw_vga)
	);     

wire	[1:0]	s_ram_rdb_mask_video;
wire	[7:0]	s_ram_rdb_mask_vga;
wire	[10:0]	s_ram_rab_mask_video;
wire	[8:0]	s_ram_rab_mask_vga;
wire	[7:0]	pixel_video ;  //blankout_video?r_ram_wdb:'d0;
wire	[7:0]	pixel_vga;


wire	hsout_vga,vsout_vga,hsout_video,blankout_vga,blankout_video;
wire	hsout = mode_vga?hsout_vga:hsout_video;
assign	vsout = mode_vga?vsout_vga:vsout_video;
wire	blankout = mode_vga?blankout_vga:blankout_video;
wire	[7:0]	pixel ;//= mode_vga?pixel_vga:pixel_video;
wire	s_req_mask_video;


sender_video sender_video0(	
	.rst(start_send & rst & !mode_vga),
	.clk(qck), 
                
	.hsin(H_sig),
	.vsin(V_sig),//V_sig
	.blankin(blank_video_send),

	.pixel(pixel_video),//pixel_video;
	        
	.send_ram_rdb_raw(s_ram_rdb_raw_video),
	.send_ram_rdb_mask(s_ram_rdb_mask_video),
	
	.send_ram_rab_raw(s_ram_rab_raw_video),
	.send_ram_rab_mask(s_ram_rab_mask_video),

	.s_req_raw(s_req_raw_video),
	.s_req_mask(s_req_mask_video),
	.s_ack_raw(s_ack),
    .s_ack_mask(s_ack_mask),
    
	.qd_in(qd)   
	);
wire	H_sig_vga,qfv_vga;
wire	[7:0]	pixel_R,pixel_G,pixel_B;
wire	s_ack_mask_vga;
wire	s_req_mask_vga;
wire	blank_NTSC;

sender_vga sender_vga0(	
	.rst(start_send & rst & mode_vga),//
	.clk(clk40m), 
                
	.hsin(H_sig_vga),
	.vsin(V_sig_vga),
	.blankin(qfv_vga),
	.blank_NTSC(blank_NTSC),

	.pixel_R(pixel_R),
	.pixel_G(pixel_G),
	.pixel_B(pixel_B),
	        
	.send_ram_rdb_raw(s_ram_rdb_raw_vga),
	.send_ram_rdb_mask(s_ram_rdb_mask_vga),
	
	.send_ram_rab_raw(s_ram_rab_raw_vga),
	.send_ram_rab_mask(s_ram_rab_mask_vga),

	.s_req_raw(s_req_raw_vga),
	.s_req_mask(s_req_mask_vga),
	
        .s_ack_raw(s_ack),
        .s_ack_mask(s_ack_mask),
        
	.hsout(hsout_vga),
	.vsout(vsout_vga),
	.blankout(blankout_vga)
	); 


vga_out vga_out0(	
	.rst(start_send & rst),
	.clk40m(clk40m),
	.hsync(H_sig_vga),
	.vsync(V_sig_vga),
//	.odd_even_out,
	.blank(qfv_vga),
	.vsin(vsync_rev),
	.blank_NTSC(blank_NTSC)
	); 

wire	[15:0]	s_ram_rdb_dsp;
wire	[8:0]	s_ram_rab_dsp;
wire	s_ram_wen_dsp;

wire [2:0]   cmd_dsp        ;
wire         cmdack_dsp     ;
wire [20:0]  addr_dsp       ;
wire [15:0]  datain_dsp     ;
wire [15:0]  dataout_dsp    ;

wire	[15:0]	s_ram_wdb_dsp;
wire	[8:0]	s_ram_wab_dsp;
wire	s_req_dsp;


wire	[7:0]	r_ram_rdb_mask;
wire	[8:0]	r_ram_rab_mask;
wire	r_req_mask;

wire	[7:0]	s_ram_wdb_mask;
wire	[8:0]	s_ram_wab_mask;

wire	s_ram_wen_mask;

wire	[15:0]	s_ram_wdb_raw;
wire	[7:0]	s_ram_wab_raw;
wire	s_req_raw;
wire	s_ram_wen_raw;

wire	s_req_mask = mode_vga ? s_req_mask_vga : s_req_mask_video;
wire	mask_send_ack;
wire	mask_mode;
wire	mask_read_ena;
datacnl_dsp datacnl_dsp0(		      
	.clk(clk),                            
	.rst(rst),                            
                                              
	.r_ram_rdb_mask(r_ram_rdb_mask),        
	.r_ram_rab_mask(r_ram_rab_mask),        
	.r_req_in_mask(r_req_mask),                
        .r_ack_mask(r_ack_mask),                                        
	
	.s_ram_wdb_mask(s_ram_wdb_mask),                                           
	.s_ram_wab_mask(s_ram_wab_mask),                          
	.s_ram_wen_mask(s_ram_wen_mask),                         
	.s_req_in_mask(s_req_mask),                              
	.s_ack_mask(s_ack_mask),                                   
	                                                                           
	.r_ram_rdb_raw(r_ram_rdb_raw),	                          
	.r_ram_rab_raw(r_ram_rab_raw),	                          
	.r_req_in_raw(r_req_raw),                                 
        .r_ack_raw(r_ack_raw),                                    
	
	.s_ram_wdb_raw(s_ram_wdb_raw),                            
	.s_ram_wab_raw(s_ram_wab_raw),                            
	.s_ram_wen_raw(s_ram_wen_raw),	                          
	.s_req_in_raw(s_req_raw),                                    
	.s_ack_raw(s_ack_raw),
		                                                          
	.cmd(cmd_dsp),
	.cmdack(cmdack_dsp),
	.addr(addr_dsp),
	.datain(datain_dsp),   
	.dataout(dataout_dsp),
                                                                         
	.start_read(start_read),
	.mode_vga_in(mode_vga),
				                                                          
	.vsync(vsync_rev), 
	.vsync_vga(!V_sig_vga),
	
	.raw_demand(raw_demand),  //1'b1 
	.raw_send_int(raw_send_int), 
	              
	.mask_demand(mask_demand),
//	.mask_mode(mask_mode) 
	.mask_send_ack(mask_send_ack),
	.mask_read_ena(mask_read_ena)   
                );
//wire	mask_receive_int = ~mask_mode;

reg	mask_send_ack_reg;
reg	mask_send_ack_reg1;
reg	mask_send_ack_reg2;
always @ (posedge qck) begin
mask_send_ack_reg <= mask_send_ack;
mask_send_ack_reg1 <= mask_send_ack_reg;
mask_send_ack_reg2 <= mask_send_ack_reg1;
end
reg	mask_receive_int;             
always @ (posedge qck or negedge rst)
if(!rst)
	mask_receive_int <= 1;
else if(mask_send_ack & (!mask_send_ack_reg2))
	mask_receive_int <= 0;
else
	mask_receive_int <= 1;
                                                     			          
wire	[10:0]	sa_dsp   ; 
wire	[1:0]	ba_dsp   ; 
wire	cs_n_dsp ; 
wire	cke_dsp  ;
wire	ras_n_dsp;
wire	cas_n_dsp; 
wire	we_n_dsp ;
wire	[15:0]	dq_dsp   ;
                                                                           
sdr_sdram_dsp sdr_sdram_dsp1(
        .CLK    (clk),
        .RESET_N(rst),
        .ADDR   (addr_dsp),
        .CMD    (cmd_dsp),
        .CMDACK (cmdack_dsp),
        .DATAIN (datain_dsp),    
        .DATAOUT(dataout_dsp),

        .SA     (sa_dsp),
        .BA     (ba_dsp),
        .CS_N   (cs_n_dsp),
        .CKE    (cke_dsp),
        .RAS_N  (ras_n_dsp),
        .CAS_N  (cas_n_dsp),
        .WE_N   (we_n_dsp),
        .DQ     (dq_dsp)
        ); 


	
ram512_8to2k_2 ram_s3( 
	.data     (s_ram_wdb_mask)  ,
	.wren     (s_ram_wen_mask)  ,
	.wraddress(s_ram_wab_mask)  ,
	.rdaddress(s_ram_rab_mask_video)  ,
	.wrclock  (clk)  ,
	.rdclock  (qck)  ,
	.q        (s_ram_rdb_mask_video)
	);
	
ram512_8 ram_s4( 
	.data     (s_ram_wdb_mask)  ,
	.wren     (s_ram_wen_mask)  ,
	.wraddress(s_ram_wab_mask)  ,
	.rdaddress(s_ram_rab_mask_vga)  ,
	.wrclock  (clk) ,
	.rdclock  (clk40m)  ,
	.q        (s_ram_rdb_mask_vga)
	);

wire	[15:0]	s_ram_rdb_raw;
wire	[9:0]	s_ram_rab_wab;

wire	[8:0]	s5_ram_rab;
wire	[7:0]	s5_ram_rdb;

ram256_16to512_8 ram_s5( 
	.data     (s_ram_wdb_raw)  ,
	.wren     (s_ram_wen_raw)  ,
	.wraddress(s_ram_wab_raw)  ,
	.rdaddress(s5_ram_rab)  ,
	.wrclock  (clk)  ,
	.rdclock  (clk_dsp)  ,//clkin
	.q        (s5_ram_rdb)
	);	

wire	[1:0]	r_ram_wdb_mask;
wire	[10:0]	r_ram_wab_mask;
wire	r_ram_wen_mask;

wire	clk80m = clkin;
wire	send_raw = ce_dsp | oe_dsp;
arbiter arbiter0(
	.rst(rst),
	
	.clk_dsp(clk_dsp),//clkin
	.db_dsp(db_dsp),
	.wr_dsp(wr_dsp),
	.rd_dsp(rd_dsp),
	
	.ce_dsp(ce_dsp),
	.oe_dsp(oe_dsp),
	.ram_rdb(s5_ram_rdb),
	.ram_rab(s5_ram_rab),
	.s_raw_req(s_req_raw),
	.s_raw_ack(s_ack_raw),	
	
	.ram_wdb(r_ram_wdb_mask),
	.ram_wab(r_ram_wab_mask),
	.ram_wen(r_ram_wen_mask),
	.r_req(r_req_mask),
	.r_ack(r_ack_mask)
	);
				
ram2k_2to512_8 ram_r3( 
	.data     (r_ram_wdb_mask),
	.wren     (r_ram_wen_mask),
	.wraddress(r_ram_wab_mask),
	.rdaddress(r_ram_rab_mask),
	.wrclock  (clk_dsp),//clkin
	.rdclock  (clk80m),
	.q        (r_ram_rdb_mask)
	);

    
endmodule