i2c_altera.hier_info

详细介绍SDRAM原理的中文电子书籍

clk => STATE12_reg.CLK
clk => STATE16_reg.CLK
clk => STATE8_reg.CLK
clk => STATE19_reg.CLK
clk => r_ram_rab[7]~reg0.CLK
clk => r_ram_rab[6]~reg0.CLK
clk => r_ram_rab[5]~reg0.CLK
clk => r_ram_rab[4]~reg0.CLK
clk => r_ram_rab[3]~reg0.CLK
clk => r_ram_rab[2]~reg0.CLK
clk => r_ram_rab[1]~reg0.CLK
clk => r_ram_rab[0]~reg0.CLK
clk => s_ram_wab_reg[7].CLK
clk => s_ram_wab_reg[6].CLK
clk => s_ram_wab_reg[5].CLK
clk => s_ram_wab_reg[4].CLK
clk => s_ram_wab_reg[3].CLK
clk => s_ram_wab_reg[2].CLK
clk => s_ram_wab_reg[1].CLK
clk => s_ram_wab_reg[0].CLK
clk => s_ram_wab_hbit.CLK
clk => start_send~reg0.CLK
clk => w_page[10].CLK
clk => w_page[9].CLK
clk => w_page[8].CLK
clk => w_page[7].CLK
clk => w_page[6].CLK
clk => w_page[5].CLK
clk => w_page[4].CLK
clk => w_page[3].CLK
clk => w_page[2].CLK
clk => w_page[1].CLK
clk => w_page[0].CLK
clk => w_ba[1].CLK
clk => w_ba[0].CLK
clk => r_page_video[10].CLK
clk => r_page_video[9].CLK
clk => r_page_video[8].CLK
clk => r_page_video[7].CLK
clk => r_page_video[6].CLK
clk => r_page_video[5].CLK
clk => r_page_video[4].CLK
clk => r_page_video[3].CLK
clk => r_page_video[2].CLK
clk => r_page_video[1].CLK
clk => r_page_video[0].CLK
clk => r_ba_video[1].CLK
clk => r_ba_video[0].CLK
clk => r_ba0_vga.CLK
clk => ba0_cnl.CLK
clk => r_ba1_vga.CLK
clk => r_ba0~reg0.CLK
clk => r_page_vga_odd[10].CLK
clk => r_page_vga_odd[9].CLK
clk => r_page_vga_odd[8].CLK
clk => r_page_vga_odd[7].CLK
clk => r_page_vga_odd[6].CLK
clk => r_page_vga_odd[5].CLK
clk => r_page_vga_odd[4].CLK
clk => r_page_vga_odd[3].CLK
clk => r_page_vga_odd[2].CLK
clk => r_page_vga_odd[1].CLK
clk => r_page_vga_odd[0].CLK
clk => r_page_vga_even[10].CLK
clk => r_page_vga_even[9].CLK
clk => r_page_vga_even[8].CLK
clk => r_page_vga_even[7].CLK
clk => r_page_vga_even[6].CLK
clk => r_page_vga_even[5].CLK
clk => r_page_vga_even[4].CLK
clk => r_page_vga_even[3].CLK
clk => r_page_vga_even[2].CLK
clk => r_page_vga_even[1].CLK
clk => r_page_vga_even[0].CLK
clk => STATE[20].CLK
clk => STATE[19].CLK
clk => STATE[18].CLK
clk => STATE[17].CLK
clk => STATE[16].CLK
clk => STATE[15].CLK
clk => STATE[14].CLK
clk => STATE[13].CLK
clk => STATE[12].CLK
clk => STATE[11].CLK
clk => STATE[10].CLK
clk => STATE[9].CLK
clk => STATE[8].CLK
clk => STATE[7].CLK
clk => STATE[6].CLK
clk => STATE[5].CLK
clk => STATE[4].CLK
clk => STATE[3].CLK
clk => STATE[2].CLK
clk => STATE[1].CLK
clk => STATE[0].CLK
clk => s_enable.CLK
clk => RCDCL_CNT[1].CLK
clk => RCDCL_CNT[0].CLK
clk => Burst_cnt[7].CLK
clk => Burst_cnt[6].CLK
clk => Burst_cnt[5].CLK
clk => Burst_cnt[4].CLK
clk => Burst_cnt[3].CLK
clk => Burst_cnt[2].CLK
clk => Burst_cnt[1].CLK
clk => Burst_cnt[0].CLK
clk => s_ack~reg0.CLK
clk => r_ack~reg0.CLK
clk => s_req1.CLK
rst => STATE[19].ACLR
rst => STATE[18].ACLR
rst => STATE[17].ACLR
rst => STATE[16].ACLR
rst => STATE[15].ACLR
rst => STATE[14].ACLR
rst => STATE[13].ACLR
rst => STATE[12].ACLR
rst => STATE[11].ACLR
rst => STATE[10].ACLR
rst => STATE[9].ACLR
rst => STATE[8].ACLR
rst => STATE[7].ACLR
rst => STATE[6].ACLR
rst => STATE[5].ACLR
rst => STATE[4].ACLR
rst => STATE[3].ACLR
rst => STATE[2].ACLR
rst => STATE[1].ACLR
rst => STATE[0].PRESET
rst => s_enable.ACLR
rst => RCDCL_CNT[1].ACLR
rst => RCDCL_CNT[0].ACLR
rst => Burst_cnt[7].ACLR
rst => Burst_cnt[6].ACLR
rst => Burst_cnt[5].ACLR
rst => Burst_cnt[4].ACLR
rst => Burst_cnt[3].ACLR
rst => Burst_cnt[2].ACLR
rst => Burst_cnt[1].ACLR
rst => Burst_cnt[0].ACLR
rst => r_ram_rab[6]~reg0.ACLR
rst => STATE[20].ACLR
rst => r_ram_rab[5]~reg0.ACLR
rst => r_ram_rab[4]~reg0.ACLR
rst => r_ram_rab[3]~reg0.ACLR
rst => r_ram_rab[2]~reg0.ACLR
rst => r_ram_rab[1]~reg0.ACLR
rst => r_ram_rab[0]~reg0.ACLR
rst => r_ack~reg0.ACLR
rst => r_ram_rab[7]~reg0.ACLR
rst => s_ram_wab_hbit.ACLR
rst => s_ram_wab_reg[6].ACLR
rst => s_ram_wab_reg[5].ACLR
rst => s_ram_wab_reg[4].ACLR
rst => s_ram_wab_reg[3].ACLR
rst => s_ram_wab_reg[2].ACLR
rst => s_ram_wab_reg[1].ACLR
rst => s_ram_wab_reg[0].ACLR
rst => s_ram_wab_reg[7].ACLR
rst => s_ack~reg0.ACLR
rst => start_send~reg0.ACLR
rst => w_page[9].ACLR
rst => w_page[8].ACLR
rst => w_page[7].ACLR
rst => w_page[6].ACLR
rst => w_page[5].ACLR
rst => w_page[4].ACLR
rst => w_page[3].ACLR
rst => w_page[2].ACLR
rst => w_page[1].ACLR
rst => w_page[0].ACLR
rst => w_page[10].ACLR
rst => w_ba[0].ACLR
rst => w_ba[1].ACLR
rst => r_page_video[9].ACLR
rst => r_page_video[8].ACLR
rst => r_page_video[7].ACLR
rst => r_page_video[6].ACLR
rst => r_page_video[5].ACLR
rst => r_page_video[4].ACLR
rst => r_page_video[3].ACLR
rst => r_page_video[2].ACLR
rst => r_page_video[1].ACLR
rst => r_page_video[0].ACLR
rst => r_page_video[10].ACLR
rst => r_ba_video[0].ACLR
rst => r_ba_video[1].ACLR
rst => ba0_cnl.ACLR
rst => r_ba0_vga.PRESET
rst => r_ba1_vga.ACLR
rst => r_page_vga_odd[9].ACLR
rst => r_page_vga_odd[8].ACLR
rst => r_page_vga_odd[7].ACLR
rst => r_page_vga_odd[6].ACLR
rst => r_page_vga_odd[5].ACLR
rst => r_page_vga_odd[4].ACLR
rst => r_page_vga_odd[3].ACLR
rst => r_page_vga_odd[2].ACLR
rst => r_page_vga_odd[1].ACLR
rst => r_page_vga_odd[0].ACLR
rst => r_page_vga_even[10].ACLR
rst => r_page_vga_even[9].ACLR
rst => r_page_vga_even[8].ACLR
rst => r_page_vga_even[7].ACLR
rst => r_page_vga_even[6].ACLR
rst => r_page_vga_even[5].ACLR
rst => r_page_vga_even[4].ACLR
rst => r_page_vga_even[3].ACLR
rst => r_page_vga_even[2].ACLR
rst => r_page_vga_even[1].ACLR
rst => r_page_vga_even[0].ACLR
rst => r_page_vga_odd[10].ACLR
r_ram_rdb[0] => datain[0].DATAIN
r_ram_rdb[1] => datain[1].DATAIN
r_ram_rdb[2] => datain[2].DATAIN
r_ram_rdb[3] => datain[3].DATAIN
r_ram_rdb[4] => datain[4].DATAIN
r_ram_rdb[5] => datain[5].DATAIN
r_ram_rdb[6] => datain[6].DATAIN
r_ram_rdb[7] => datain[7].DATAIN
r_ram_rdb[8] => datain[8].DATAIN
r_ram_rdb[9] => datain[9].DATAIN
r_ram_rdb[10] => datain[10].DATAIN
r_ram_rdb[11] => datain[11].DATAIN
r_ram_rdb[12] => datain[12].DATAIN
r_ram_rdb[13] => datain[13].DATAIN
r_ram_rdb[14] => datain[14].DATAIN
r_ram_rdb[15] => datain[15].DATAIN
r_ram_rdb[16] => datain[16].DATAIN
r_ram_rdb[17] => datain[17].DATAIN
r_ram_rdb[18] => datain[18].DATAIN
r_ram_rdb[19] => datain[19].DATAIN
r_ram_rdb[20] => datain[20].DATAIN
r_ram_rdb[21] => datain[21].DATAIN
r_ram_rdb[22] => datain[22].DATAIN
r_ram_rdb[23] => datain[23].DATAIN
r_ram_rdb[24] => datain[24].DATAIN
r_ram_rdb[25] => datain[25].DATAIN
r_ram_rdb[26] => datain[26].DATAIN
r_ram_rdb[27] => datain[27].DATAIN
r_ram_rdb[28] => datain[28].DATAIN
r_ram_rdb[29] => datain[29].DATAIN
r_ram_rdb[30] => datain[30].DATAIN
r_ram_rdb[31] => datain[31].DATAIN
r_ram_rab[0] <= r_ram_rab[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[1] <= r_ram_rab[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[2] <= r_ram_rab[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[3] <= r_ram_rab[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[4] <= r_ram_rab[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[5] <= r_ram_rab[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[6] <= r_ram_rab[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_ram_rab[7] <= r_ram_rab[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_req_in => r_req1.DATAIN
r_ack <= r_ack~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_busy => always18~0.IN1
s_ram_wdb[0] <= s_ram_wdb[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[1] <= s_ram_wdb[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[2] <= s_ram_wdb[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[3] <= s_ram_wdb[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[4] <= s_ram_wdb[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[5] <= s_ram_wdb[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[6] <= s_ram_wdb[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[7] <= s_ram_wdb[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[8] <= s_ram_wdb[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[9] <= s_ram_wdb[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[10] <= s_ram_wdb[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[11] <= s_ram_wdb[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[12] <= s_ram_wdb[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[13] <= s_ram_wdb[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[14] <= s_ram_wdb[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[15] <= s_ram_wdb[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[16] <= s_ram_wdb[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[17] <= s_ram_wdb[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[18] <= s_ram_wdb[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[19] <= s_ram_wdb[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[20] <= s_ram_wdb[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[21] <= s_ram_wdb[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[22] <= s_ram_wdb[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[23] <= s_ram_wdb[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[24] <= s_ram_wdb[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[25] <= s_ram_wdb[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[26] <= s_ram_wdb[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[27] <= s_ram_wdb[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[28] <= s_ram_wdb[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[29] <= s_ram_wdb[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[30] <= s_ram_wdb[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wdb[31] <= s_ram_wdb[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[0] <= s_ram_wab_reg[0].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[1] <= s_ram_wab_reg[1].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[2] <= s_ram_wab_reg[2].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[3] <= s_ram_wab_reg[3].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[4] <= s_ram_wab_reg[4].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[5] <= s_ram_wab_reg[5].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[6] <= s_ram_wab_reg[6].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[7] <= s_ram_wab_reg[7].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab[8] <= s_ram_wab_hbit.DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[0] <= s_ram_wab_reg[0].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[1] <= s_ram_wab_reg[1].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[2] <= s_ram_wab_reg[2].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[3] <= s_ram_wab_reg[3].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[4] <= s_ram_wab_reg[4].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[5] <= s_ram_wab_reg[5].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[6] <= s_ram_wab_reg[6].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wab_video[7] <= s_ram_wab_reg[7].DB_MAX_OUTPUT_PORT_TYPE
s_ram_wen <= s_enable.DB_MAX_OUTPUT_PORT_TYPE
s_req_in => s_req1.DATAIN
s_ack <= s_ack~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd[0] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
cmd[1] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
cmd[2] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
cmdack => always5~0.IN1
cmdack => always7~0.IN0
cmdack => always14~0.IN1
cmdack => Select~18.IN1
cmdack => Select~16.IN1
cmdack => Select~14.IN1
cmdack => Select~12.IN1
cmdack => Select~10.IN1
cmdack => Burst_cnt~0.OUTPUTSELECT
cmdack => Burst_cnt~1.OUTPUTSELECT
cmdack => Burst_cnt~2.OUTPUTSELECT
cmdack => Burst_cnt~3.OUTPUTSELECT
cmdack => Burst_cnt~4.OUTPUTSELECT
cmdack => Burst_cnt~5.OUTPUTSELECT
cmdack => Burst_cnt~6.OUTPUTSELECT
cmdack => Burst_cnt~7.OUTPUTSELECT
cmdack => Select~8.IN1
cmdack => Select~2.IN1
cmdack => Select~12.IN2
cmdack => Select~6.IN1
cmdack => Select~4.IN1
cmdack => Select~0.IN1
cmdack => Select~12.IN3
cmdack => Select~0.IN3
cmdack => Select~1.IN3
cmdack => Select~2.IN3
cmdack => Select~3.IN3
cmdack => Select~5.IN2
cmdack => Select~7.IN3
cmdack => Select~9.IN3
cmdack => Select~11.IN3
cmdack => Select~13.IN3
cmdack => Select~15.IN3
cmdack => Select~17.IN3
cmdack => Select~19.IN3
addr[0] <= addr~2.DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= reduce_or~34.DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= reduce_or~34.DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= reduce_nor~12.DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= addr~1.DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= reduce_or~34.DB_MAX_OUTPUT_PORT_TYPE
addr[6] <= reduce_nor~10.DB_MAX_OUTPUT_PORT_TYPE
addr[7] <= reduce_nor~10.DB_MAX_OUTPUT_PORT_TYPE
addr[8] <= Select~44.DB_MAX_OUTPUT_PORT_TYPE
addr[9] <= Select~43.DB_MAX_OUTPUT_PORT_TYPE
addr[10] <= Select~42.DB_MAX_OUTPUT_PORT_TYPE
addr[11] <= Select~41.DB_MAX_OUTPUT_PORT_TYPE
addr[12] <= Select~40.DB_MAX_OUTPUT_PORT_TYPE
addr[13] <= Select~39.DB_MAX_OUTPUT_PORT_TYPE
addr[14] <= Select~38.DB_MAX_OUTPUT_PORT_TYPE
addr[15] <= Select~37.DB_MAX_OUTPUT_PORT_TYPE
addr[16] <= Select~36.DB_MAX_OUTPUT_PORT_TYPE
addr[17] <= Select~35.DB_MAX_OUTPUT_PORT_TYPE
addr[18] <= Select~34.DB_MAX_OUTPUT_PORT