i2c_altera.hier_info

详细介绍SDRAM原理的中文电子书籍

wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
rdaddress[0] => rdaddress[0]~7.IN1
rdaddress[1] => rdaddress[1]~6.IN1
rdaddress[2] => rdaddress[2]~5.IN1
rdaddress[3] => rdaddress[3]~4.IN1
rdaddress[4] => rdaddress[4]~3.IN1
rdaddress[5] => rdaddress[5]~2.IN1
rdaddress[6] => rdaddress[6]~1.IN1
rdaddress[7] => rdaddress[7]~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b
q[13] <= altsyncram:altsyncram_component.q_b
q[14] <= altsyncram:altsyncram_component.q_b
q[15] <= altsyncram:altsyncram_component.q_b
q[16] <= altsyncram:altsyncram_component.q_b
q[17] <= altsyncram:altsyncram_component.q_b
q[18] <= altsyncram:altsyncram_component.q_b
q[19] <= altsyncram:altsyncram_component.q_b
q[20] <= altsyncram:altsyncram_component.q_b
q[21] <= altsyncram:altsyncram_component.q_b
q[22] <= altsyncram:altsyncram_component.q_b
q[23] <= altsyncram:altsyncram_component.q_b
q[24] <= altsyncram:altsyncram_component.q_b
q[25] <= altsyncram:altsyncram_component.q_b
q[26] <= altsyncram:altsyncram_component.q_b
q[27] <= altsyncram:altsyncram_component.q_b
q[28] <= altsyncram:altsyncram_component.q_b
q[29] <= altsyncram:altsyncram_component.q_b
q[30] <= altsyncram:altsyncram_component.q_b
q[31] <= altsyncram:altsyncram_component.q_b


|I2C_ALTERA|mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component
wren_a => altsyncram_l951:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_l951:auto_generated.data_a[0]
data_a[1] => altsyncram_l951:auto_generated.data_a[1]
data_a[2] => altsyncram_l951:auto_generated.data_a[2]
data_a[3] => altsyncram_l951:auto_generated.data_a[3]
data_a[4] => altsyncram_l951:auto_generated.data_a[4]
data_a[5] => altsyncram_l951:auto_generated.data_a[5]
data_a[6] => altsyncram_l951:auto_generated.data_a[6]
data_a[7] => altsyncram_l951:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
address_a[0] => altsyncram_l951:auto_generated.address_a[0]
address_a[1] => altsyncram_l951:auto_generated.address_a[1]
address_a[2] => altsyncram_l951:auto_generated.address_a[2]
address_a[3] => altsyncram_l951:auto_generated.address_a[3]
address_a[4] => altsyncram_l951:auto_generated.address_a[4]
address_a[5] => altsyncram_l951:auto_generated.address_a[5]
address_a[6] => altsyncram_l951:auto_generated.address_a[6]
address_a[7] => altsyncram_l951:auto_generated.address_a[7]
address_a[8] => altsyncram_l951:auto_generated.address_a[8]
address_a[9] => altsyncram_l951:auto_generated.address_a[9]
address_b[0] => altsyncram_l951:auto_generated.address_b[0]
address_b[1] => altsyncram_l951:auto_generated.address_b[1]
address_b[2] => altsyncram_l951:auto_generated.address_b[2]
address_b[3] => altsyncram_l951:auto_generated.address_b[3]
address_b[4] => altsyncram_l951:auto_generated.address_b[4]
address_b[5] => altsyncram_l951:auto_generated.address_b[5]
address_b[6] => altsyncram_l951:auto_generated.address_b[6]
address_b[7] => altsyncram_l951:auto_generated.address_b[7]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_l951:auto_generated.clock0
clock1 => altsyncram_l951:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_l951:auto_generated.q_b[0]
q_b[1] <= altsyncram_l951:auto_generated.q_b[1]
q_b[2] <= altsyncram_l951:auto_generated.q_b[2]
q_b[3] <= altsyncram_l951:auto_generated.q_b[3]
q_b[4] <= altsyncram_l951:auto_generated.q_b[4]
q_b[5] <= altsyncram_l951:auto_generated.q_b[5]
q_b[6] <= altsyncram_l951:auto_generated.q_b[6]
q_b[7] <= altsyncram_l951:auto_generated.q_b[7]
q_b[8] <= altsyncram_l951:auto_generated.q_b[8]
q_b[9] <= altsyncram_l951:auto_generated.q_b[9]
q_b[10] <= altsyncram_l951:auto_generated.q_b[10]
q_b[11] <= altsyncram_l951:auto_generated.q_b[11]
q_b[12] <= altsyncram_l951:auto_generated.q_b[12]
q_b[13] <= altsyncram_l951:auto_generated.q_b[13]
q_b[14] <= altsyncram_l951:auto_generated.q_b[14]
q_b[15] <= altsyncram_l951:auto_generated.q_b[15]
q_b[16] <= altsyncram_l951:auto_generated.q_b[16]
q_b[17] <= altsyncram_l951:auto_generated.q_b[17]
q_b[18] <= altsyncram_l951:auto_generated.q_b[18]
q_b[19] <= altsyncram_l951:auto_generated.q_b[19]
q_b[20] <= altsyncram_l951:auto_generated.q_b[20]
q_b[21] <= altsyncram_l951:auto_generated.q_b[21]
q_b[22] <= altsyncram_l951:auto_generated.q_b[22]
q_b[23] <= altsyncram_l951:auto_generated.q_b[23]
q_b[24] <= altsyncram_l951:auto_generated.q_b[24]
q_b[25] <= altsyncram_l951:auto_generated.q_b[25]
q_b[26] <= altsyncram_l951:auto_generated.q_b[26]
q_b[27] <= altsyncram_l951:auto_generated.q_b[27]
q_b[28] <= altsyncram_l951:auto_generated.q_b[28]
q_b[29] <= altsyncram_l951:auto_generated.q_b[29]
q_b[30] <= altsyncram_l951:auto_generated.q_b[30]
q_b[31] <= altsyncram_l951:auto_generated.q_b[31]


|I2C_ALTERA|mesure_card_top:inst5|ram1k_8to256_32:ram_r0|altsyncram:altsyncram_component|altsyncram_l951:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a0.PORTBDATAOUT1
q_b[9] <= ram_block1a1.PORTBDATAOUT1
q_b[10] <= ram_block1a2.PORTBDATAOUT1
q_b[11] <= ram_block1a3.PORTBDATAOUT1
q_b[12] <= ram_block1a4.PORTBDATAOUT1
q_b[13] <= ram_block1a5.PORTBDATAOUT1
q_b[14] <= ram_block1a6.PORTBDATAOUT1
q_b[15] <= ram_block1a7.PORTBDATAOUT1
q_b[16] <= ram_block1a0.PORTBDATAOUT2
q_b[17] <= ram_block1a1.PORTBDATAOUT2
q_b[18] <= ram_block1a2.PORTBDATAOUT2
q_b[19] <= ram_block1a3.PORTBDATAOUT2
q_b[20] <= ram_block1a4.PORTBDATAOUT2
q_b[21] <= ram_block1a5.PORTBDATAOUT2
q_b[22] <= ram_block1a6.PORTBDATAOUT2
q_b[23] <= ram_block1a7.PORTBDATAOUT2
q_b[24] <= ram_block1a0.PORTBDATAOUT3
q_b[25] <= ram_block1a1.PORTBDATAOUT3
q_b[26] <= ram_block1a2.PORTBDATAOUT3
q_b[27] <= ram_block1a3.PORTBDATAOUT3
q_b[28] <= ram_block1a4.PORTBDATAOUT3
q_b[29] <= ram_block1a5.PORTBDATAOUT3
q_b[30] <= ram_block1a6.PORTBDATAOUT3
q_b[31] <= ram_block1a7.PORTBDATAOUT3
wren_a => ram_block1a0.ENA0