i2c_altera.hier_info

详细介绍SDRAM原理的中文电子书籍

|I2C_ALTERA
ENC_CLK <= PCLK.DB_MAX_OUTPUT_PORT_TYPE
PCLK => ENC_CLK.DATAIN
PCLK => CLK_27M.DATAIN
PCLK => mesure_card_top:inst5.qck
PCLK => Y2Cb:inst12.clk
CLK_27M <= PCLK.DB_MAX_OUTPUT_PORT_TYPE
SDRAM_CLK <= clk80m.DB_MAX_OUTPUT_PORT_TYPE
SYSCLK => PLL:inst3.inclk0
SYSCLK => filter:inst8.clk
SYSCLK => SAA_ROM:inst2.clock
SYSCLK => N_REG:inst13.clock
SYSCLK => ENC_ROM:inst22.clock
SYSCLK => Led_run:inst21.clk
SRAM_CE_N <= <VCC>
SRAM_OE_N <= <VCC>
SRAM_WE_N <= <VCC>
SDRAM_CAS_N <= mesure_card_top:inst5.cas_n
RST => mesure_card_top:inst5.rst
RST => Y2Cb:inst12.rst
RST => clk_gen:inst19.rst
RST => filter:inst8.rst_in
RST => Led_run:inst21.rst
P_HS => mesure_card_top:inst5.H_sig
P_VS => mesure_card_top:inst5.V_sig
VideoLock => mesure_card_top:inst5.lock
db_dsp22[0] <= mesure_card_top:inst5.db_dsp[0]
db_dsp22[1] <= mesure_card_top:inst5.db_dsp[1]
db_dsp22[2] <= mesure_card_top:inst5.db_dsp[2]
db_dsp22[3] <= mesure_card_top:inst5.db_dsp[3]
db_dsp22[4] <= mesure_card_top:inst5.db_dsp[4]
db_dsp22[5] <= mesure_card_top:inst5.db_dsp[5]
db_dsp22[6] <= mesure_card_top:inst5.db_dsp[6]
db_dsp22[7] <= mesure_card_top:inst5.db_dsp[7]
db_dsp22[8] <= mesure_card_top:inst5.db_dsp[8]
db_dsp22[9] <= mesure_card_top:inst5.db_dsp[9]
db_dsp22[10] <= mesure_card_top:inst5.db_dsp[10]
db_dsp22[11] <= mesure_card_top:inst5.db_dsp[11]
db_dsp22[12] <= mesure_card_top:inst5.db_dsp[12]
db_dsp22[13] <= mesure_card_top:inst5.db_dsp[13]
db_dsp22[14] <= mesure_card_top:inst5.db_dsp[14]
db_dsp22[15] <= mesure_card_top:inst5.db_dsp[15]
SDRAM_DQ[0] <= mesure_card_top:inst5.dq[0]
SDRAM_DQ[1] <= mesure_card_top:inst5.dq[1]
SDRAM_DQ[2] <= mesure_card_top:inst5.dq[2]
SDRAM_DQ[3] <= mesure_card_top:inst5.dq[3]
SDRAM_DQ[4] <= mesure_card_top:inst5.dq[4]
SDRAM_DQ[5] <= mesure_card_top:inst5.dq[5]
SDRAM_DQ[6] <= mesure_card_top:inst5.dq[6]
SDRAM_DQ[7] <= mesure_card_top:inst5.dq[7]
SDRAM_DQ[8] <= mesure_card_top:inst5.dq[8]
SDRAM_DQ[9] <= mesure_card_top:inst5.dq[9]
SDRAM_DQ[10] <= mesure_card_top:inst5.dq[10]
SDRAM_DQ[11] <= mesure_card_top:inst5.dq[11]
SDRAM_DQ[12] <= mesure_card_top:inst5.dq[12]
SDRAM_DQ[13] <= mesure_card_top:inst5.dq[13]
SDRAM_DQ[14] <= mesure_card_top:inst5.dq[14]
SDRAM_DQ[15] <= mesure_card_top:inst5.dq[15]
SDRAM_DQ[16] <= mesure_card_top:inst5.dq[16]
SDRAM_DQ[17] <= mesure_card_top:inst5.dq[17]
SDRAM_DQ[18] <= mesure_card_top:inst5.dq[18]
SDRAM_DQ[19] <= mesure_card_top:inst5.dq[19]
SDRAM_DQ[20] <= mesure_card_top:inst5.dq[20]
SDRAM_DQ[21] <= mesure_card_top:inst5.dq[21]
SDRAM_DQ[22] <= mesure_card_top:inst5.dq[22]
SDRAM_DQ[23] <= mesure_card_top:inst5.dq[23]
SDRAM_DQ[24] <= mesure_card_top:inst5.dq[24]
SDRAM_DQ[25] <= mesure_card_top:inst5.dq[25]
SDRAM_DQ[26] <= mesure_card_top:inst5.dq[26]
SDRAM_DQ[27] <= mesure_card_top:inst5.dq[27]
SDRAM_DQ[28] <= mesure_card_top:inst5.dq[28]
SDRAM_DQ[29] <= mesure_card_top:inst5.dq[29]
SDRAM_DQ[30] <= mesure_card_top:inst5.dq[30]
SDRAM_DQ[31] <= mesure_card_top:inst5.dq[31]
dq_dsp[0] <= mesure_card_top:inst5.dq_dsp[0]
dq_dsp[1] <= mesure_card_top:inst5.dq_dsp[1]
dq_dsp[2] <= mesure_card_top:inst5.dq_dsp[2]
dq_dsp[3] <= mesure_card_top:inst5.dq_dsp[3]
dq_dsp[4] <= mesure_card_top:inst5.dq_dsp[4]
dq_dsp[5] <= mesure_card_top:inst5.dq_dsp[5]
dq_dsp[6] <= mesure_card_top:inst5.dq_dsp[6]
dq_dsp[7] <= mesure_card_top:inst5.dq_dsp[7]
dq_dsp[8] <= mesure_card_top:inst5.dq_dsp[8]
dq_dsp[9] <= mesure_card_top:inst5.dq_dsp[9]
dq_dsp[10] <= mesure_card_top:inst5.dq_dsp[10]
dq_dsp[11] <= mesure_card_top:inst5.dq_dsp[11]
dq_dsp[12] <= mesure_card_top:inst5.dq_dsp[12]
dq_dsp[13] <= mesure_card_top:inst5.dq_dsp[13]
dq_dsp[14] <= mesure_card_top:inst5.dq_dsp[14]
dq_dsp[15] <= mesure_card_top:inst5.dq_dsp[15]
PDATA[0] => Y2Cb:inst12.qd[0]
PDATA[1] => Y2Cb:inst12.qd[1]
PDATA[2] => Y2Cb:inst12.qd[2]
PDATA[3] => Y2Cb:inst12.qd[3]
PDATA[4] => Y2Cb:inst12.qd[4]
PDATA[5] => Y2Cb:inst12.qd[5]
PDATA[6] => Y2Cb:inst12.qd[6]
PDATA[7] => Y2Cb:inst12.qd[7]
SDRAM_CKE <= mesure_card_top:inst5.cke
SDRAM_CS_N <= mesure_card_top:inst5.cs_n
SDRAM_RAS_N <= mesure_card_top:inst5.ras_n
SDRAM_WE_N <= mesure_card_top:inst5.we_n
FLASH_CE_N <= <VCC>
FLASH_WE_N <= <VCC>
FLASH_OE_N <= <VCC>
SCL <= I2C:inst1.SCL
SDA <= I2C:inst1.SDA
SCL_ENC <= I2C:inst17.SCL
NP_SEL => rom_sel:inst20.i2c_id
SDA_ENC <= I2C:inst17.SDA
ENC_DATA[0] <= mesure_card_top:inst5.pixel_video[0]
ENC_DATA[1] <= mesure_card_top:inst5.pixel_video[1]
ENC_DATA[2] <= mesure_card_top:inst5.pixel_video[2]
ENC_DATA[3] <= mesure_card_top:inst5.pixel_video[3]
ENC_DATA[4] <= mesure_card_top:inst5.pixel_video[4]
ENC_DATA[5] <= mesure_card_top:inst5.pixel_video[5]
ENC_DATA[6] <= mesure_card_top:inst5.pixel_video[6]
ENC_DATA[7] <= mesure_card_top:inst5.pixel_video[7]
LEDG[0] <= Led_run:inst21.led[0]
LEDG[1] <= Led_run:inst21.led[1]
LEDG[2] <= Led_run:inst21.led[2]
LEDG[3] <= Led_run:inst21.led[3]
SDRAM_A[0] <= mesure_card_top:inst5.sa[0]
SDRAM_A[1] <= mesure_card_top:inst5.sa[1]
SDRAM_A[2] <= mesure_card_top:inst5.sa[2]
SDRAM_A[3] <= mesure_card_top:inst5.sa[3]
SDRAM_A[4] <= mesure_card_top:inst5.sa[4]
SDRAM_A[5] <= mesure_card_top:inst5.sa[5]
SDRAM_A[6] <= mesure_card_top:inst5.sa[6]
SDRAM_A[7] <= mesure_card_top:inst5.sa[7]
SDRAM_A[8] <= mesure_card_top:inst5.sa[8]
SDRAM_A[9] <= mesure_card_top:inst5.sa[9]
SDRAM_A[10] <= mesure_card_top:inst5.sa[10]
SDRAM_A[11] <= <GND>
SDRAM_BA[0] <= mesure_card_top:inst5.ba[0]
SDRAM_BA[1] <= mesure_card_top:inst5.ba[1]
SDRAM_DQM[0] <= mesure_card_top:inst5.dqm[0]
SDRAM_DQM[1] <= mesure_card_top:inst5.dqm[1]
SDRAM_DQM[2] <= mesure_card_top:inst5.dqm[2]
SDRAM_DQM[3] <= mesure_card_top:inst5.dqm[3]
ENC_HS => ~NO_FANOUT~
ENC_VS => ~NO_FANOUT~
mode_vga => ~NO_FANOUT~
dsp_rst => ~NO_FANOUT~
pal_ntsc_flag => ~NO_FANOUT~


|I2C_ALTERA|PLL:inst3
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
locked <= altpll:altpll_component.locked


|I2C_ALTERA|PLL:inst3|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= pll.CLK3
clk[4] <= pll.CLK4
clk[5] <= pll.CLK5
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|I2C_ALTERA|mesure_card_top:inst5
clkin => clk80m.IN12
rst => rst~0.IN8
H_sig => H_sig~0.IN3
V_sig => V_sig~0.IN2
odd_even_sig => odd_even_sig~0.IN1
qd[0] => qd[0]~7.IN2
qd[1] => qd[1]~6.IN2
qd[2] => qd[2]~5.IN2
qd[3] => qd[3]~4.IN2
qd[4] => qd[4]~3.IN2
qd[5] => qd[5]~2.IN2
qd[6] => qd[6]~1.IN2
qd[7] => qd[7]~0.IN2
qck => qck~0.IN8
pixel_video[0] <= sender_video:sender_video0.pixel
pixel_video[1] <= sender_video:sender_video0.pixel
pixel_video[2] <= sender_video:sender_video0.pixel
pixel_video[3] <= sender_video:sender_video0.pixel
pixel_video[4] <= sender_video:sender_video0.pixel
pixel_video[5] <= sender_video:sender_video0.pixel
pixel_video[6] <= sender_video:sender_video0.pixel
pixel_video[7] <= sender_video:sender_video0.pixel
hsout_vga <= sender_vga:sender_vga0.hsout
vsout_vga <= sender_vga:sender_vga0.vsout
pixel_R[0] <= sender_vga:sender_vga0.pixel_R
pixel_R[1] <= sender_vga:sender_vga0.pixel_R
pixel_R[2] <= sender_vga:sender_vga0.pixel_R
pixel_R[3] <= sender_vga:sender_vga0.pixel_R
pixel_R[4] <= sender_vga:sender_vga0.pixel_R
pixel_R[5] <= sender_vga:sender_vga0.pixel_R
pixel_R[6] <= sender_vga:sender_vga0.pixel_R
pixel_R[7] <= sender_vga:sender_vga0.pixel_R
pixel_G[0] <= sender_vga:sender_vga0.pixel_G
pixel_G[1] <= sender_vga:sender_vga0.pixel_G
pixel_G[2] <= sender_vga:sender_vga0.pixel_G
pixel_G[3] <= sender_vga:sender_vga0.pixel_G
pixel_G[4] <= sender_vga:sender_vga0.pixel_G
pixel_G[5] <= sender_vga:sender_vga0.pixel_G
pixel_G[6] <= sender_vga:sender_vga0.pixel_G
pixel_G[7] <= sender_vga:sender_vga0.pixel_G
pixel_B[0] <= sender_vga:sender_vga0.pixel_B
pixel_B[1] <= sender_vga:sender_vga0.pixel_B
pixel_B[2] <= sender_vga:sender_vga0.pixel_B
pixel_B[3] <= sender_vga:sender_vga0.pixel_B
pixel_B[4] <= sender_vga:sender_vga0.pixel_B
pixel_B[5] <= sender_vga:sender_vga0.pixel_B
pixel_B[6] <= sender_vga:sender_vga0.pixel_B
pixel_B[7] <= sender_vga:sender_vga0.pixel_B
blankout_vga <= sender_vga:sender_vga0.blankout
dq[0] <= sdr_sdram:sdr_sdram1.DQ
dq[1] <= sdr_sdram:sdr_sdram1.DQ
dq[2] <= sdr_sdram:sdr_sdram1.DQ
dq[3] <= sdr_sdram:sdr_sdram1.DQ
dq[4] <= sdr_sdram:sdr_sdram1.DQ
dq[5] <= sdr_sdram:sdr_sdram1.DQ
dq[6] <= sdr_sdram:sdr_sdram1.DQ
dq[7] <= sdr_sdram:sdr_sdram1.DQ
dq[8] <= sdr_sdram:sdr_sdram1.DQ
dq[9] <= sdr_sdram:sdr_sdram1.DQ
dq[10] <= sdr_sdram:sdr_sdram1.DQ
dq[11] <= sdr_sdram:sdr_sdram1.DQ
dq[12] <= sdr_sdram:sdr_sdram1.DQ
dq[13] <= sdr_sdram:sdr_sdram1.DQ
dq[14] <= sdr_sdram:sdr_sdram1.DQ
dq[15] <= sdr_sdram:sdr_sdram1.DQ
dq[16] <= sdr_sdram:sdr_sdram1.DQ
dq[17] <= sdr_sdram:sdr_sdram1.DQ
dq[18] <= sdr_sdram:sdr_sdram1.DQ
dq[19] <= sdr_sdram:sdr_sdram1.DQ
dq[20] <= sdr_sdram:sdr_sdram1.DQ
dq[21] <= sdr_sdram:sdr_sdram1.DQ
dq[22] <= sdr_sdram:sdr_sdram1.DQ
dq[23] <= sdr_sdram:sdr_sdram1.DQ
dq[24] <= sdr_sdram:sdr_sdram1.DQ
dq[25] <= sdr_sdram:sdr_sdram1.DQ
dq[26] <= sdr_sdram:sdr_sdram1.DQ
dq[27] <= sdr_sdram:sdr_sdram1.DQ
dq[28] <= sdr_sdram:sdr_sdram1.DQ
dq[29] <= sdr_sdram:sdr_sdram1.DQ
dq[30] <= sdr_sdram:sdr_sdram1.DQ
dq[31] <= sdr_sdram:sdr_sdram1.DQ
sa[0] <= sdr_sdram:sdr_sdram1.SA
sa[1] <= sdr_sdram:sdr_sdram1.SA
sa[2] <= sdr_sdram:sdr_sdram1.SA
sa[3] <= sdr_sdram:sdr_sdram1.SA
sa[4] <= sdr_sdram:sdr_sdram1.SA
sa[5] <= sdr_sdram:sdr_sdram1.SA
sa[6] <= sdr_sdram:sdr_sdram1.SA
sa[7] <= sdr_sdram:sdr_sdram1.SA
sa[8] <= sdr_sdram:sdr_sdram1.SA
sa[9] <= sdr_sdram:sdr_sdram1.SA
sa[10] <= sdr_sdram:sdr_sdram1.SA
ba[0] <= sdr_sdram:sdr_sdram1.BA
ba[1] <= sdr_sdram:sdr_sdram1.BA
cke <= sdr_sdram:sdr_sdram1.CKE
cs_n <= sdr_sdram:sdr_sdram1.CS_N
ras_n <= sdr_sdram:sdr_sdram1.RAS_N
cas_n <= sdr_sdram:sdr_sdram1.CAS_N
we_n <= sdr_sdram:sdr_sdram1.WE_N
sdram_clk <= <GND>
dqm[0] <= <GND>
dqm[1] <= <GND>
dqm[2] <= <GND>
dqm[3] <= <GND>
mode_vga => mode_vga~0.IN3
dq_dsp[0] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[1] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[2] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[3] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[4] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[5] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[6] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[7] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[8] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[9] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[10] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[11] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[12] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[13] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[14] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
dq_dsp[15] <= sdr_sdram_dsp:sdr_sdram_dsp1.DQ
sa_dsp[0] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[1] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[2] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[3] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[4] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[5] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[6] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[7] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[8] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[9] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
sa_dsp[10] <= sdr_sdram_dsp:sdr_sdram_dsp1.SA
ba_dsp[0] <= sdr_sdram_dsp:sdr_sdram_dsp1.BA
ba_dsp[1] <= sdr_sdram_dsp:sdr_sdram_dsp1.BA
cke_dsp <= sdr_sdram_dsp:sdr_sdram_dsp1.CKE
cs_n_dsp <= sdr_sdram_dsp:sdr_sdram_dsp1.CS_N
ras_n_dsp <= sdr_sdram_dsp:sdr_sdram_dsp1.RAS_N
cas_n_dsp <= sdr_sdram_dsp:sdr_sdram_dsp1.CAS_N
we_n_dsp <= sdr_sdram_dsp:sdr_sdram_dsp1.WE_N
clk40m => clk40m~0.IN4
lock => lock_reg.DATAIN
clk_dsp => clk_dsp~0.IN3
db_dsp[0] <= arbiter:arbiter0.db_dsp
db_dsp[1] <= arbiter:arbiter0.db_dsp
db_dsp[2] <= arbiter:arbiter0.db_dsp
db_dsp[3] <= arbiter:arbiter0.db_dsp
db_dsp[4] <= arbiter:arbiter0.db_dsp
db_dsp[5] <= arbiter:arbiter0.db_dsp
db_dsp[6] <= arbiter:arbiter0.db_dsp
db_dsp[7] <= arbiter:arbiter0.db_dsp
db_dsp[8] <= arbiter:arbiter0.db_dsp
db_dsp[9] <= arbiter:arbiter0.db_dsp
db_dsp[10] <= arbiter:arbiter0.db_dsp
db_dsp[11] <= arbiter:arbiter0.db_dsp
db_dsp[12] <= arbiter:arbiter0.db_dsp
db_dsp[13] <= arbiter:arbiter0.db_dsp
db_dsp[14] <= arbiter:arbiter0.db_dsp
db_dsp[15] <= arbiter:arbiter0.db_dsp
wr_dsp => wr_dsp~0.IN1
rd_dsp => rd_dsp~0.IN1
oe_dsp => oe_dsp~0.IN1
ce_dsp => ce_dsp~0.IN1
raw_demand => raw_demand~0.IN1
raw_send_int <= datacnl_dsp:datacnl_dsp0.raw_send_int