i2c_altera.map.qmsg

详细介绍SDRAM原理的中文电子书籍

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram256_16to512_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram256_16to512_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram256_16to512_8 " "Info: Found entity 1: ram256_16to512_8" {  } { { "ram256_16to512_8.v" "" { Text "D:/RedLogic/VBuffer/ram256_16to512_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2k_4to512_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram2k_4to512_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram2k_4to512_16 " "Info: Found entity 1: ram2k_4to512_16" {  } { { "ram2k_4to512_16.v" "" { Text "D:/RedLogic/VBuffer/ram2k_4to512_16.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_16to1024_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_16to1024_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_16to1024_8 " "Info: Found entity 1: ram512_16to1024_8" {  } { { "ram512_16to1024_8.v" "" { Text "D:/RedLogic/VBuffer/ram512_16to1024_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_16to1k_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_16to1k_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_16to1k_8 " "Info: Found entity 1: ram512_16to1k_8" {  } { { "ram512_16to1k_8.v" "" { Text "D:/RedLogic/VBuffer/ram512_16to1k_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_16to2k_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_16to2k_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_16to2k_4 " "Info: Found entity 1: ram512_16to2k_4" {  } { { "ram512_16to2k_4.v" "" { Text "D:/RedLogic/VBuffer/ram512_16to2k_4.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_32to2k_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_32to2k_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_32to2k_8 " "Info: Found entity 1: ram512_32to2k_8" {  } { { "ram512_32to2k_8.v" "" { Text "D:/RedLogic/VBuffer/ram512_32to2k_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_8 " "Info: Found entity 1: ram512_8" {  } { { "ram512_8.v" "" { Text "D:/RedLogic/VBuffer/ram512_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_8to256_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_8to256_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_8to256_16 " "Info: Found entity 1: ram512_8to256_16" {  } { { "ram512_8to256_16.v" "" { Text "D:/RedLogic/VBuffer/ram512_8to256_16.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receiver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 receiver " "Info: Found entity 1: receiver" {  } { { "receiver.v" "" { Text "D:/RedLogic/VBuffer/receiver.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_data_path.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Info: Found entity 1: sdr_data_path" {  } { { "sdr_data_path.v" "" { Text "D:/RedLogic/VBuffer/sdr_data_path.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params_dsp.v(35) " "Warning: (10274) Verilog HDL macro warning at params_dsp.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params_dsp.v" "" { Text "D:/RedLogic/VBuffer/params_dsp.v" 35 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_data_path_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_data_path_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path_dsp " "Info: Found entity 1: sdr_data_path_dsp" {  } { { "sdr_data_path_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_data_path_dsp.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params.v(35) " "Warning: (10274) Verilog HDL macro warning at params.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params.v" "" { Text "D:/RedLogic/VBuffer/params.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_ack sdr_sdram.v(116) " "Warning: Verilog HDL net warning at sdr_sdram.v(116): created undeclared net \"ref_ack\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "cm_ack sdr_sdram.v(117) " "Warning: Verilog HDL net warning at sdr_sdram.v(117): created undeclared net \"cm_ack\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_req sdr_sdram.v(130) " "Warning: Verilog HDL net warning at sdr_sdram.v(130): created undeclared net \"ref_req\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(192) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(192): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(193) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(193): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 193 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(194) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(194): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 194 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(195) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(195): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 195 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_sdram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_sdram " "Info: Found entity 1: sdr_sdram" {  } { { "sdr_sdram.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MACRO_REDEFINITION" "DSIZE params_dsp.v(35) " "Warning: (10274) Verilog HDL macro warning at params_dsp.v(35): overriding existing definition for macro \"DSIZE\"" {  } { { "params_dsp.v" "" { Text "D:/RedLogic/VBuffer/params_dsp.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_ack sdr_sdram_dsp.v(116) " "Warning: Verilog HDL net warning at sdr_sdram_dsp.v(116): created undeclared net \"ref_ack\"" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "cm_ack sdr_sdram_dsp.v(117) " "Warning: Verilog HDL net warning at sdr_sdram_dsp.v(117): created undeclared net \"cm_ack\"" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_req sdr_sdram_dsp.v(130) " "Warning: Verilog HDL net warning at sdr_sdram_dsp.v(130): created undeclared net \"ref_req\"" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram_dsp.v(192) " "Warning: (10273) Verilog HDL warning at sdr_sdram_dsp.v(192): extended using \"x\" or \"z\"" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram_dsp.v(193) " "Warning: (10273) Verilog HDL warning at sdr_sdram_dsp.v(193): extended using \"x\" or \"z\"" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 193 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_sdram_dsp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_sdram_dsp.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_sdram_dsp " "Info: Found entity 1: sdr_sdram_dsp" {  } { { "sdr_sdram_dsp.v" "" { Text "D:/RedLogic/VBuffer/sdr_sdram_dsp.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sender_vga.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sender_vga.v" { { "Info" "ISGN_ENTITY_NAME" "1 sender_vga " "Info: Found entity 1: sender_vga" {  } { { "sender_vga.v" "" { Text "D:/RedLogic/VBuffer/sender_vga.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sender_video.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sender_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 sender_video " "Info: Found entity 1: sender_video" {  } { { "sender_video.v" "" { Text "D:/RedLogic/VBuffer/sender_video.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "filter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 filter " "Info: Found entity 1: filter" {  } { { "filter.v" "" { Text "D:/RedLogic/VBuffer/filter.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C.TDF 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C.TDF" { { "Info" "ISGN_ENTITY_NAME" "1 I2C " "Info: Found entity 1: I2C" {  } { { "I2C.TDF" "" { Text "D:/RedLogic/VBuffer/I2C.TDF" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_ALTERA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_ALTERA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_ALTERA " "Info: Found entity 1: I2C_ALTERA" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.v" "" { Text "D:/RedLogic/VBuffer/clk_div.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Info: Found entity 1: clk_gen" {  } { { "clk_gen.v" "" { Text "D:/RedLogic/VBuffer/clk_gen.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gen_sync.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gen_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 gen_sync " "Info: Found entity 1: gen_sync" {  } { { "gen_sync.v" "" { Text "D:/RedLogic/VBuffer/gen_sync.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "I2C_ALTERA " "Info: Elaborating entity \"I2C_ALTERA\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "GEN_S 32'b00000000000000000000000000000001 " "Warning: Can't find a definition for parameter GEN_S -- assuming 32'b00000000000000000000000000000001 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "S_WAIT 32'b00000000000000000000000000000010 " "Warning: Can't find a definition for parameter S_WAIT -- assuming 32'b00000000000000000000000000000010 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "SUBADDR 32'b00000000000000000000000000000101 " "Warning: Can't find a definition for parameter SUBADDR -- assuming 32'b00000000000000000000000000000101 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "SUBADDR_ACK 32'b00000000000000000000000000000110 " "Warning: Can't find a definition for parameter SUBADDR_ACK -- assuming 32'b00000000000000000000000000000110 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "DATA 32'b00000000000000000000000000000111 " "Warning: Can't find a definition for parameter DATA -- assuming 32'b00000000000000000000000000000111 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "DATA_ACK 32'b00000000000000000000000000001000 " "Warning: Can't find a definition for parameter DATA_ACK -- assuming 32'b00000000000000000000000000001000 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_UNRESOLVED_PARAMETER" "GEN_P 32'b00000000000000000000000000001001 " "Warning: Can't find a definition for parameter GEN_P -- assuming 32'b00000000000000000000000000001001 was intended to be a quoted string" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1024 856 1056 1184 "inst" "" } } } }  } 0}