mux_vab.tdf

详细介绍SDRAM原理的中文电子书籍

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=5 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 10 
SUBDESIGN mux_vab
( 
	data[19..0]	:	input;
	result[4..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[4..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data183w[3..0]	: WIRE;
	w_data213w[3..0]	: WIRE;
	w_data238w[3..0]	: WIRE;
	w_data263w[3..0]	: WIRE;
	w_data288w[3..0]	: WIRE;
	w_result184w	: WIRE;
	w_result194w	: WIRE;
	w_result195w	: WIRE;
	w_result214w	: WIRE;
	w_result224w	: WIRE;
	w_result225w	: WIRE;
	w_result239w	: WIRE;
	w_result249w	: WIRE;
	w_result250w	: WIRE;
	w_result264w	: WIRE;
	w_result274w	: WIRE;
	w_result275w	: WIRE;
	w_result289w	: WIRE;
	w_result299w	: WIRE;
	w_result300w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result289w, w_result264w, w_result239w, w_result214w, w_result184w);
	sel_node[] = ( sel[1..0]);
	w_data183w[] = ( data[15..15], data[10..10], data[5..5], data[0..0]);
	w_data213w[] = ( data[16..16], data[11..11], data[6..6], data[1..1]);
	w_data238w[] = ( data[17..17], data[12..12], data[7..7], data[2..2]);
	w_data263w[] = ( data[18..18], data[13..13], data[8..8], data[3..3]);
	w_data288w[] = ( data[19..19], data[14..14], data[9..9], data[4..4]);
	w_result184w = w_result194w;
	w_result194w = (((w_data183w[1..1] & sel_node[0..0]) & (! w_result195w)) # (w_result195w & (w_data183w[3..3] # (! sel_node[0..0]))));
	w_result195w = (((w_data183w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data183w[2..2])));
	w_result214w = w_result224w;
	w_result224w = (((w_data213w[1..1] & sel_node[0..0]) & (! w_result225w)) # (w_result225w & (w_data213w[3..3] # (! sel_node[0..0]))));
	w_result225w = (((w_data213w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data213w[2..2])));
	w_result239w = w_result249w;
	w_result249w = (((w_data238w[1..1] & sel_node[0..0]) & (! w_result250w)) # (w_result250w & (w_data238w[3..3] # (! sel_node[0..0]))));
	w_result250w = (((w_data238w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data238w[2..2])));
	w_result264w = w_result274w;
	w_result274w = (((w_data263w[1..1] & sel_node[0..0]) & (! w_result275w)) # (w_result275w & (w_data263w[3..3] # (! sel_node[0..0]))));
	w_result275w = (((w_data263w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data263w[2..2])));
	w_result289w = w_result299w;
	w_result299w = (((w_data288w[1..1] & sel_node[0..0]) & (! w_result300w)) # (w_result300w & (w_data288w[3..3] # (! sel_node[0..0]))));
	w_result300w = (((w_data288w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data288w[2..2])));
END;
--VALID FILE