mux_tab.tdf

详细介绍SDRAM原理的中文电子书籍

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=3 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 6 
SUBDESIGN mux_tab
( 
	data[11..0]	:	input;
	result[2..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[2..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data155w[3..0]	: WIRE;
	w_data185w[3..0]	: WIRE;
	w_data210w[3..0]	: WIRE;
	w_result156w	: WIRE;
	w_result166w	: WIRE;
	w_result167w	: WIRE;
	w_result186w	: WIRE;
	w_result196w	: WIRE;
	w_result197w	: WIRE;
	w_result211w	: WIRE;
	w_result221w	: WIRE;
	w_result222w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result211w, w_result186w, w_result156w);
	sel_node[] = ( sel[1..0]);
	w_data155w[] = ( data[9..9], data[6..6], data[3..3], data[0..0]);
	w_data185w[] = ( data[10..10], data[7..7], data[4..4], data[1..1]);
	w_data210w[] = ( data[11..11], data[8..8], data[5..5], data[2..2]);
	w_result156w = w_result166w;
	w_result166w = (((w_data155w[1..1] & sel_node[0..0]) & (! w_result167w)) # (w_result167w & (w_data155w[3..3] # (! sel_node[0..0]))));
	w_result167w = (((w_data155w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data155w[2..2])));
	w_result186w = w_result196w;
	w_result196w = (((w_data185w[1..1] & sel_node[0..0]) & (! w_result197w)) # (w_result197w & (w_data185w[3..3] # (! sel_node[0..0]))));
	w_result197w = (((w_data185w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data185w[2..2])));
	w_result211w = w_result221w;
	w_result221w = (((w_data210w[1..1] & sel_node[0..0]) & (! w_result222w)) # (w_result222w & (w_data210w[3..3] # (! sel_node[0..0]))));
	w_result222w = (((w_data210w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data210w[2..2])));
END;
--VALID FILE