i2c_altera.fit.qmsg

详细介绍SDRAM原理的中文电子书籍

{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 PLL:inst3\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"PLL:inst3\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "PLL.v" "" { Text "D:/RedLogic/VBuffer/PLL.v" 87 -1 0 } } { "I2C_ALTERA.bdf" "" { Schematic "D:/RedLogic/VBuffer/I2C_ALTERA.bdf" { { 1472 496 752 1648 "inst3" "" } } } }  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "USER_PB\[0\] " "Warning: Node \"USER_PB\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "USER_PB\[0\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "USER_PB\[1\] " "Warning: Node \"USER_PB\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "USER_PB\[1\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "USER_PB\[2\] " "Warning: Node \"USER_PB\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "USER_PB\[2\]" } } } }  } 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "USER_PB\[3\] " "Warning: Node \"USER_PB\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "USER_PB\[3\]" } } } }  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:14 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:14" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.970 ns register memory " "Info: Estimated most critical path is register to memory delay of 0.970 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_cmd:inst\|rom_addr\[1\] 1 REG LAB_X32_Y13 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X32_Y13; Fanout = 14; REG Node = 'i2c_cmd:inst\|rom_addr\[1\]'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "" { i2c_cmd:inst|rom_addr[1] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/RedLogic/VBuffer/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.383 ns) 0.970 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg1 2 MEM M4K_X33_Y13 1 " "Info: 2: + IC(0.587 ns) + CELL(0.383 ns) = 0.970 ns; Loc. = M4K_X33_Y13; Fanout = 1; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_eas:auto_generated\|ram_block1a7~porta_address_reg1'" {  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "0.970 ns" { i2c_cmd:inst|rom_addr[1] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_eas.tdf" "" { Text "D:/RedLogic/VBuffer/db/altsyncram_eas.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 39.48 % " "Info: Total cell delay = 0.383 ns ( 39.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns 60.52 % " "Info: Total interconnect delay = 0.587 ns ( 60.52 % )" {  } {  } 0}  } { { "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/RedLogic/VBuffer/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/RedLogic/VBuffer/db/I2C_ALTERA.quartus_db" { Floorplan "D:/RedLogic/VBuffer/" "" "0.970 ns" { i2c_cmd:inst|rom_addr[1] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_eas:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:43 " "Info: Fitter placement operations ending: elapsed time is 00:00:43" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}