i2c_altera.fit.eqn

详细介绍SDRAM原理的中文电子书籍

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--Z1__clk0 is PLL:inst3|altpll:altpll_component|_clk0 at PLL_2
Z1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(SYSCLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Z1__clk1 is PLL:inst3|altpll:altpll_component|_clk1 at PLL_2
Z1__clk1 = PLL.CLK1(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(SYSCLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--PB1_CAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|CAS_N at LC_X18_Y15_N2
--operation mode is normal

PB1_CAS_N_lut_out = DC1_CAS_N;
PB1_CAS_N = DFFEAS(PB1_CAS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_CS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|CS_N at LC_X35_Y18_N4
--operation mode is normal

PB1_CS_N_lut_out = GND;
PB1_CS_N = DFFEAS(PB1_CS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , DC1_CS_N, , , VCC);


--PB1_RAS_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|RAS_N at LC_X18_Y15_N8
--operation mode is normal

PB1_RAS_N_lut_out = DC1_RAS_N;
PB1_RAS_N = DFFEAS(PB1_RAS_N_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--PB1_WE_N is mesure_card_top:inst5|sdr_sdram:sdr_sdram1|WE_N at LC_X18_Y15_N9
--operation mode is normal

PB1_WE_N_lut_out = DC1_WE_N;
PB1_WE_N = DFFEAS(PB1_WE_N_lut_out, GLOBAL(Z1__clk0), VCC, , , , , , );


--TC1_q_b[0] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[0] at M4K_X33_Y17
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 33, Port A Logical Width: 8, Port B Logical Depth: 33, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0] = TC1_q_b[0]_PORT_B_data_out_reg[0];

--TC1_q_b[7] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[7] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[7] = TC1_q_b[0]_PORT_B_data_out_reg[7];

--TC1_q_b[6] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[6] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[6] = TC1_q_b[0]_PORT_B_data_out_reg[6];

--TC1_q_b[5] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[5] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[5] = TC1_q_b[0]_PORT_B_data_out_reg[5];

--TC1_q_b[4] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[4] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[4] = TC1_q_b[0]_PORT_B_data_out_reg[4];

--TC1_q_b[3] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[3] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[3] = TC1_q_b[0]_PORT_B_data_out_reg[3];

--TC1_q_b[2] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[2] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[2] = TC1_q_b[0]_PORT_B_data_out_reg[2];

--TC1_q_b[1] is mesure_card_top:inst5|sender_video:sender_video0|altshift_taps:qd_reg_dly2_rtl_0|shift_taps_hkg:auto_generated|altsyncram_2uu:altsyncram2|q_b[1] at M4K_X33_Y17
TC1_q_b[0]_PORT_A_data_in = BUS(SB1_qd_reg_dly1[7], SB1_qd_reg_dly1[6], SB1_qd_reg_dly1[5], SB1_qd_reg_dly1[4], SB1_qd_reg_dly1[3], SB1_qd_reg_dly1[2], SB1_qd_reg_dly1[1], SB1_qd_reg_dly1[0]);
TC1_q_b[0]_PORT_A_data_in_reg = DFFE(TC1_q_b[0]_PORT_A_data_in, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_A_address_reg = DFFE(TC1_q_b[0]_PORT_A_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_address = BUS(UC1_safe_q[0], UC1_safe_q[1], UC1_safe_q[2], UC1_safe_q[3], UC1_safe_q[4], UC1_safe_q[5]);
TC1_q_b[0]_PORT_B_address_reg = DFFE(TC1_q_b[0]_PORT_B_address, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_A_write_enable = VCC;
TC1_q_b[0]_PORT_A_write_enable_reg = DFFE(TC1_q_b[0]_PORT_A_write_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_PORT_B_read_enable = VCC;
TC1_q_b[0]_PORT_B_read_enable_reg = DFFE(TC1_q_b[0]_PORT_B_read_enable, TC1_q_b[0]_clock_0, , , );
TC1_q_b[0]_clock_0 = GLOBAL(PCLK);
TC1_q_b[0]_PORT_B_data_out = MEMORY(TC1_q_b[0]_PORT_A_data_in_reg, , TC1_q_b[0]_PORT_A_address_reg, TC1_q_b[0]_PORT_B_address_reg, TC1_q_b[0]_PORT_A_write_enable_reg, TC1_q_b[0]_PORT_B_read_enable_reg, , , TC1_q_b[0]_clock_0, , , , , );
TC1_q_b[0]_PORT_B_data_out_reg = DFFE(TC1_q_b[0]_PORT_B_data_out, TC1_q_b[0]_clock_0, , , );
TC1_q_b[1] = TC1_q_b[0]_PORT_B_data_out_reg[1];


--SB1L64 is mesure_card_top:inst5|sender_video:sender_video0|pixel[7]~64 at LC_X35_Y17_N3
--operation mode is normal

SB1_blank_dly36_qfbk = SB1_blank_dly36;
SB1L64 = SB1_blank_dly36_qfbk & SB1_pixel_out[7] # !SB1_blank_dly36_qfbk & (TC1_q_b[0]);

--SB1_blank_dly36 is mesure_card_top:inst5|sender_video:sender_video0|blank_dly36 at LC_X35_Y17_N3
--operation mode is normal

SB1_blank_dly36 = DFFEAS(SB1L64, GLOBAL(PCLK), VCC, , , SB1_blank_dly35, , , VCC);


--SB1L54 is mesure_card_top:inst5|sender_video:sender_video0|pixel[6]~65 at LC_X35_Y17_N9
--operation mode is normal

SB1L54 = SB1_blank_dly36 & SB1_pixel_out[6] # !SB1_blank_dly36 & (TC1_q_b[1]);


--SB1L44 is mesure_card_top:inst5|sender_video:sender_video0|pixel[5]~66 at LC_X35_Y17_N5
--operation mode is normal

SB1L44 = SB1_blank_dly36 & (SB1_pixel_out[5]) # !SB1_blank_dly36 & TC1_q_b[2];


--SB1L34 is mesure_card_top:inst5|sender_video:sender_video0|pixel[4]~67 at LC_X35_Y17_N6
--operation mode is normal

SB1L34 = SB1_blank_dly36 & (SB1_pixel_out[4]) # !SB1_blank_dly36 & TC1_q_b[3];


--SB1L24 is mesure_card_top:inst5|sender_video:sender_video0|pixel[3]~68 at LC_X35_Y17_N2