i2c_altera.fit.rpt

详细介绍SDRAM原理的中文电子书籍

; Total memory bits     ; 27,912 / 239,616 ( 11 % )                     ;
; Total PLLs            ; 1 / 2 ( 50 % )                                ;
+-----------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C12Q240C8                   ;                                ;
; Use smart compilation                              ; On                             ; Off                            ;
; Fitter Effort                                      ; Standard Fit                   ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Extra                          ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+----------------------------------------------+-----------------------------------------+
; Option                                       ; Setting                                 ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                                     ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                     ;
; Enable device-wide output enable (DEV_OE)    ; Off                                     ;
; Enable INIT_DONE output                      ; Off                                     ;
; Configuration scheme                         ; Active Serial                           ;
; Error detection CRC                          ; Off                                     ;
; Reserve ASDO pin after configuration.        ; As output driving an unspecified signal ;
; Reserve all unused pins                      ; As input tri-stated                     ;
; Base pin-out file on sameframe device        ; Off                                     ;
+----------------------------------------------+-----------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                            ;
+-----------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------+------------------+
; Node                                                                                    ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                                                                                    ; Destination Port ;
+-----------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------+------------------+
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[7]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[7] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[6]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[6] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[5]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[5] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[4]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[4] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[3]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[3] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[2]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[2] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[1]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[1] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|arbiter:arbiter0|db_dsp_reg[0]                                    ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|ram256_16to512_8:ram_s5|altsyncram:altsyncram_component|altsyncram_1751:auto_generated|q_b[0] ; PORTBDATAOUT     ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[1]                             ; PORTBDATAOUT     ;
; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; mesure_card_top:inst5|sdr_sdram_dsp:sdr_sdram_dsp1|sdr_data_path_dsp:data_path1|DIN1[0]                             ; PORTBDATAOUT     ;