sender_video.v

详细介绍SDRAM原理的中文电子书籍

`timescale 1ns / 1ns

module sender_video(	
	rst,						//main reset
	clk,				     	       //system clock
                
	hsin,
	vsin,
	blankin,

	pixel,
	        
	send_ram_rdb_raw,
	send_ram_rdb_mask,
	
	send_ram_rab_raw,
	send_ram_rab_mask,
               
	s_req_raw,
	s_ack_raw,
        
	s_req_mask,
	s_ack_mask,
	
	qd_in
              );						


/***input and output ***/
input	rst, clk;
input	hsin,vsin,blankin;

input	[7:0]	send_ram_rdb_raw;
input	[1:0]	send_ram_rdb_mask;
input	s_ack_mask;
input	s_ack_raw;

output	[7:0]	pixel;
output	[9:0]	send_ram_rab_raw;
output	[10:0]	send_ram_rab_mask;

output	s_req_raw;
output	s_req_mask;

input	[7:0]	qd_in;

reg	s_req_raw;
reg	[7:0]	pixel_out;


//define the dram pixels(one line)
parameter  DRAM_PIXEL    = 'd256;//H_PIXELS>>1;//'d320
//define the state machine state,using one-hot coding
parameter	IDLE     =   6'b000001,
		SEND1    =   6'b000010,
		SEND2    =   6'b000100,
		SEND3    =   6'b001000,
		SEND4    =   6'b010000,
		SEND5    =   6'b100000;

reg	hsout_reg,hsout,vsout_reg,vsout;


reg	[7:0]	qd_reg,qd_reg_dly1,qd_reg_dly2,qd_reg_dly3,qd_reg_dly4,qd_reg_dly5,qd_reg_dly6,qd_reg_dly7,qd_reg_dly8,qd_reg_dly9,
        qd_reg_dly10,qd_reg_dly11,qd_reg_dly12,qd_reg_dly13,qd_reg_dly14,qd_reg_dly15,qd_reg_dly16,qd_reg_dly17,qd_reg_dly18,qd_reg_dly19,
        qd_reg_dly20,qd_reg_dly21,qd_reg_dly22,qd_reg_dly23,qd_reg_dly24,qd_reg_dly25,qd_reg_dly26,qd_reg_dly27,qd_reg_dly28,qd_reg_dly29,
        qd_reg_dly30,qd_reg_dly31,qd_reg_dly32,qd_reg_dly33,qd_reg_dly34,qd_reg_dly35,qd_reg_dly36;

reg     blank_dly1,blank_dly2,blank_dly3,blank_dly4,blank_dly5,blank_dly6,blank_dly7,blank_dly8,blank_dly9,
        blank_dly10,blank_dly11,blank_dly12,blank_dly13,blank_dly14,blank_dly15,blank_dly16,blank_dly17,blank_dly18,blank_dly19,      
        blank_dly20,blank_dly21,blank_dly22,blank_dly23,blank_dly24,blank_dly25,blank_dly26,blank_dly27,blank_dly28,blank_dly29,
        blank_dly30,blank_dly31,blank_dly32,blank_dly33,blank_dly34,blank_dly35,blank_dly36;      
always @ (posedge clk) begin
	hsout_reg <= hsin;
	hsout <= hsout_reg;
	
	vsout_reg <= vsin;
	vsout <= vsout_reg;
	
	blank_dly1 <= blankin;
	blank_dly2 <= blank_dly1;
	blank_dly3 <= blank_dly2;
	blank_dly4 <= blank_dly3;
	blank_dly5 <= blank_dly4;
	blank_dly6 <= blank_dly5;
	blank_dly7 <= blank_dly6;
	blank_dly8 <= blank_dly7;
	blank_dly9 <= blank_dly8;
	blank_dly10 <= blank_dly9;
	blank_dly11 <= blank_dly10;
	blank_dly12 <= blank_dly11;
	blank_dly13 <= blank_dly12;
	blank_dly14 <= blank_dly13;
	blank_dly15 <= blank_dly14;
	blank_dly16 <= blank_dly15;
	blank_dly17 <= blank_dly16;
	blank_dly18 <= blank_dly17;
	blank_dly19 <= blank_dly18;
	blank_dly20 <= blank_dly19;
	blank_dly21 <= blank_dly20;
	blank_dly22 <= blank_dly21;
	blank_dly23 <= blank_dly22;
	blank_dly24 <= blank_dly23;
	blank_dly25 <= blank_dly24;
	blank_dly26 <= blank_dly25;
	blank_dly27 <= blank_dly26;
	blank_dly28 <= blank_dly27;
	blank_dly29 <= blank_dly28;
	blank_dly30 <= blank_dly29;	
   	blank_dly31 <= blank_dly30;
	blank_dly32 <= blank_dly31;
	blank_dly33 <= blank_dly32;
	blank_dly34 <= blank_dly33;
	blank_dly35 <= blank_dly34;
	blank_dly36 <= blank_dly35;
	
	qd_reg_dly1 <= qd_in;
	qd_reg_dly2 <= qd_reg_dly1;
	qd_reg_dly3 <= qd_reg_dly2;
	qd_reg_dly4 <= qd_reg_dly3;
	qd_reg_dly5 <= qd_reg_dly4;
	qd_reg_dly6 <= qd_reg_dly5;
	qd_reg_dly7 <= qd_reg_dly6;
	qd_reg_dly8 <= qd_reg_dly7;
	qd_reg_dly9 <= qd_reg_dly8;
	qd_reg_dly10 <= qd_reg_dly9;
	qd_reg_dly11 <= qd_reg_dly10;
	qd_reg_dly12 <= qd_reg_dly11;
	qd_reg_dly13 <= qd_reg_dly12;
	qd_reg_dly14 <= qd_reg_dly13;
	qd_reg_dly15 <= qd_reg_dly14;
	qd_reg_dly16 <= qd_reg_dly15;
	qd_reg_dly17 <= qd_reg_dly16;
	qd_reg_dly18 <= qd_reg_dly17;
	qd_reg_dly19 <= qd_reg_dly18;
	qd_reg_dly20 <= qd_reg_dly19;
	qd_reg_dly21 <= qd_reg_dly20;
	qd_reg_dly22 <= qd_reg_dly21;
	qd_reg_dly23 <= qd_reg_dly22;
	qd_reg_dly24 <= qd_reg_dly23;
	qd_reg_dly25 <= qd_reg_dly24;
	qd_reg_dly26 <= qd_reg_dly25;
	qd_reg_dly27 <= qd_reg_dly26;
	qd_reg_dly28 <= qd_reg_dly27;
	qd_reg_dly29 <= qd_reg_dly28;
	qd_reg_dly30 <= qd_reg_dly29;
	qd_reg_dly31 <= qd_reg_dly30;
	qd_reg_dly32 <= qd_reg_dly31;
	qd_reg_dly33 <= qd_reg_dly32;
	qd_reg_dly34 <= qd_reg_dly33;
	qd_reg_dly35 <= qd_reg_dly34;
	qd_reg_dly36 <= qd_reg_dly35;	
	end

	
reg	[9:0]	send_ram_rab_reg;
reg	send_ram_rab_hbit;


always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_reg <= 0;
else if(blank_dly34) begin
	if(send_ram_rab_reg == 'd719)
		send_ram_rab_reg <= 0;
	else
		send_ram_rab_reg <= send_ram_rab_reg + 1;
	end
else
	send_ram_rab_reg <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_hbit <= 0;
else if(send_ram_rab_reg == 'd719)
	send_ram_rab_hbit <= ~send_ram_rab_hbit;
else if(!vsout)
	send_ram_rab_hbit <= 0;

wire	[10:0]	send_ram_rab_mask = {send_ram_rab_hbit,send_ram_rab_reg};
wire	[9:0]	send_ram_rab_raw = send_ram_rab_reg;

always @ (posedge clk or negedge rst)
if(!rst)
	s_req_raw <= 0;
else if(send_ram_rab_reg=='d680 || (vsout_reg & !vsout))
	s_req_raw <= 1;
else if(s_ack_raw)
	s_req_raw <= 0;

reg	s_req_mask;
always @ (posedge clk or negedge rst)
if(!rst)
	s_req_mask <= 0;
else if(send_ram_rab_reg=='d680 || (vsout_reg & !vsout))
	s_req_mask <= 1;
else if(s_ack_mask)
	s_req_mask <= 0;
	
wire	[7:0] 	pixel = blank_dly36 ? pixel_out : qd_reg_dly36;//qd_in;//pixel_out ;
always @ (posedge clk) begin
	pixel_out <= send_ram_rdb_raw  ;//send_ram_rdb_mask
	end
endmodule