gen_sync.v

来自「详细介绍SDRAM原理的中文电子书籍」· Verilog 代码 · 共 85 行

module gen_sync(rst,pclk,href,vref,hsync,vsync);
input rst,pclk,href,vref;
output hsync,vsync;
reg hsync,vsync;

reg[7:0] Hcnt,Vcnt;
reg[3:0] State,VState;

always @(negedge pclk or negedge rst)
begin
  if(!rst)
    begin
    hsync <= 'b0;
    Hcnt <= 'b0;
    State<= 'b0;
    end
   else
    case (State)
    0:  begin
        if(href)
         begin
         State <= 'd1;
         hsync <= 'b1;
         Hcnt <= 'd0;
         end
        else
         State <= 'd0;
        end
    1:  begin
        Hcnt <= Hcnt + 1;
        if(Hcnt < 'd10)
           State <= 'd1;
        else
           State <= 'd2;
        end
    2:  begin
        hsync <= 'b0;
        if(href)
          State <= 'd2;
        else
          State <= 'd0;
        end
    default: State <= 'd0;
    endcase
end

always @(negedge href or negedge rst)
begin
  if(!rst)
    begin
    vsync <= 'b0;
    Vcnt <= 'b0;
    VState<= 'b0;
    end
   else
    case (VState)
    0:  begin
        if(vref)
         begin
         VState <= 'd1;
         vsync <= 'b1;
         Vcnt <= 'd0;
         end
        else
         VState <= 'd0;
        end
    1:  begin
        Vcnt <= Vcnt + 1;
        if(Vcnt < 'd5)
           VState <= 'd1;
        else
           VState <= 'd2;
        end
    2:  begin
        vsync <= 'b0;
        if(vref)
          VState <= 'd2;
        else
          VState <= 'd0;
        end
    default: VState <= 'd0;
    endcase
end

endmodule