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📄 pcm32.mdl

📁 PCM编码failed to translatefailed to translatefailed to translate
💻 MDL
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	      Version		      "1.4.0"
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      IncDataTypeInIds	      off
	      MangleLength	      1
	      CustomSymbolStrGlobalVar "$R$N$M"
	      CustomSymbolStrType     "$N$R$M"
	      CustomSymbolStrField    "$N$M"
	      CustomSymbolStrFcn      "$R$N$M$F"
	      CustomSymbolStrBlkIO    "rtb_$N$M"
	      CustomSymbolStrTmpVar   "$N$M"
	      CustomSymbolStrMacro    "$R$N$M"
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		16
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"GenerateTestInterfaces"
		Cell			"ModelStepFunctionPrototypeControlCompliant"
		Cell			"CPPClassGenCompliant"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		Cell			"PortableWordSizes"
		PropName		"DisabledProps"
	      }
	      Version		      "1.4.0"
	      TargetFcnLib	      "ansi_tfl_table_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      TargetFunctionLibrary   "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      GenerateTestInterfaces  off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      CompOptLevelCompliant   on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      ERTFirstTimeCompliant   off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      EnableShiftOperators    on
	      ParenthesesLevel	      "Nominal"
	      PortableWordSizes	      off
	      ModelStepFunctionPrototypeControlCompliant off
	      AutosarCompliant	      off
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      ExtModeIntrfLevel	      "Level1"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	hdlcoderui.hdlcc {
	  $ObjectID		  11
	  Description		  "HDL Coder custom configuration component"
	  Version		  "1.4.0"
	  Name			  "HDL Coder"
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    ""
	    PropName		    "HDLConfigFile"
	  }
	  HDLCActiveTab		  "0"
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      CombinatorialLogic
      TruthTable	      "[0 0;0 1;0 1;1 0;0 1;1 0;1 0;1 1]"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      DataTypeConversion
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit via back propagation"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Inherit via back propagation"
      LockScale		      off
      ConvertRealWorld	      "Real World Value (RWV)"
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Demux
      Outputs		      "4"
      DisplayOption	      "none"
      BusSelectionMode	      off
    }
    Block {
      BlockType		      Gain
      Gain		      "1"
      Multiplication	      "Element-wise(K.*u)"
      ParamMin		      "[]"
      ParamMax		      "[]"
      ParameterDataTypeMode   "Same as input"
      ParameterDataType	      "fixdt(1,16,0)"
      ParameterScalingMode    "Best Precision: Matrix-wise"
      ParameterScaling	      "[]"
      ParamDataTypeStr	      "Inherit: Same as input"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Same as input"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Same as input"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      IconShape		      "rectangular"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimization)"
      LogicDataType	      "uint(8)"
      OutDataTypeStr	      "Inherit: Logical (see Configuration Parameters: Optimization)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Reference
    }
    Block {
      BlockType		      Scope
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
      SaveToWorkspace	      off
      SaveName		      "ScopeData"
      LimitDataPoints	      on
      MaxDataPoints	      "5000"
      Decimation	      "1"
      SampleInput	      off
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Selector
      NumberOfDimensions      "1"
      IndexMode		      "One-based"
      InputPortWidth	      "-1"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
      SFunctionDeploymentMode off
    }
    Block {
      BlockType		      StateSpace
      A			      "1"
      B			      "1"
      C			      "1"
      D			      "1"
      X0		      "0"
      AbsoluteTolerance	      "auto"
      ContinuousStateAttributes	"''"
      Realization	      "auto"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      "FromPortIcon"
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      CheckFcnCallInpInsideContextMsg off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      CollapseMode	      "All dimensions"
      CollapseDim	      "1"
      InputSameDT	      on
      AccumDataTypeStr	      "Inherit: Inherit via internal rule"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Same as first input"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Terminator
    }
    Block {
      BlockType		      FrameConversion
      InheritSamplingMode     off
      OutFrame		      "Frame-based"
    }
    Block {
      BlockType		      Reshape
      OutputDimensionality    "1-D array"
      OutputDimensions	      "[1,1]"
    }
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      SamplingMode	      "Sample based"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "fixdt(1,16,0)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Inherit from 'Constant value'"
      SampleTime	      "inf"
      FramePeriod	      "inf"
    }
    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Configuration Parameters: Optimization)"
      LogicDataType	      "uint(8)"
      OutDataTypeStr	      "Inherit: Logical (see Configuration Parameters: Optimization)"
      ZeroCross		      on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Sin
      SineType		      "Time based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Bias		      "0"
      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
      Offset		      "0"
      SampleTime	      "-1"
      VectorParams1D	      on
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"

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