📄 s3c2450_fil.c
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{
NF_CE_H(nBank);
NF_SET_CLK(DUMMY_R_TACLS, DUMMY_R_TWRPH0, DUMMY_R_TWRPH1); // Don't set clk to (0, 0, 0) !!! Decoding error occurs
#if (NAND_TRANS_MODE == ASM)
if (SECTORS_PER_PAGE == 4)
{
_Write_Dummy_468Byte_AllFF();
}
else if (SECTORS_PER_PAGE == 8)
{
_Write_Dummy_428Byte_AllFF();
}
#elif (NAND_TRANS_MODE == DMA)
Write_Dummy_468Byte_AllFF_DMA();
#endif
//NAND_MSG((_T("[FIL]++Read_Spare_MLC_5(%d)\r\n"), nPpn));
NF_SET_CLK(DEFAULT_TACLS, DEFAULT_TWRPH0, DEFAULT_TWRPH1);
NF_CE_L(nBank);
//NF_MECC_Lock(); // Do NOT Lock MECC when using 4-bit ECC Decoding
// Read Spare ECC
NF_CLEAR_ECC_DEC_DONE();
if (bCheckAllFF)
{
NF_CE_H(nBank);
NF_SET_CLK(DUMMY_R_TACLS, DUMMY_R_TWRPH0, DUMMY_R_TWRPH1); // Don't set clk to (0, 0, 0) !!! Decoding error occurs
NF_DATA_W4(ECCVAL_ALLFF0); // All 0xFF ECC
NF_DATA_W4(ECCVAL_ALLFF1);
NF_SET_CLK(DEFAULT_TACLS, DEFAULT_TWRPH0, DEFAULT_TWRPH1);
NF_CE_L(nBank);
}
else
{
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Read 8 byte Spare ECC data, ->ASECC[0]
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Actually after read 7th byte, ECC decoding starts!!, ->ASECC[1]
}
// Wait Spare ECC Compare Done
NF_WAIT_ECC_DEC_DONE();
//NAND_MSG((_T(" dbg(0x%x), Cnt : %d\r\n"), pNANDFConReg->NFSTAT,i));
pSBuf =(UINT8*) &(pSpareCxt[NAND_SCXT_OFFSET/4]);
nRet = Decoding_SpareECC(pSBuf);
if (bCheckAllFF)
{
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Read 8 byte Spare ECC data ->ASECC[0]
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Actually after read 7th byte, ECC decoding starts!! ->ASECC[1]
// NAND_MSG((_T("[FIL]++Read_Spare_MLC_8(%d)\r\n"), nPpn));
}
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Read 2nd Spare ECC ->ASECC[2]
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // Actually after read 7th byte, ECC decoding starts!! ->ASECC[3]
//NAND_MSG((_T("[FIL]++Read_Spare_MLC_9(%d)\r\n"), nPpn));
_B_CheckMore:
// 2nd Try
if (nRet == ECC_UNCORRECTABLE_ERROR)
{
NAND_ERR((_T("[FIL:ERR] Read_Spare() : ECC Uncorrectable Error in Spare of Page %d 1st Time : 0x%x\r\n"), nPpn, nRet));
if (bCheckMore == TRUE32) NAND_ERR((_T("[FIL:ERR] Read_Spare() : Try ECC Decoding again with 2nd SECC copy\r\n")));
else NAND_ERR((_T("[FIL:ERR] Read_Spare() : Try ECC Decoding again with SECC bit change\r\n")));
nOffset = BYTES_PER_MAIN_PAGE+NAND_SCXT_OFFSET; // Position to SpareData
NF_CMD(CMD_RANDOM_DATA_OUTPUT);
NF_ADDR(nOffset&0xFF);
NF_ADDR((nOffset>>8)&0xFF);
NF_CMD(CMD_RANDOM_DATA_OUTPUT_CONFIRM);
// Initialize 4-bit ECC Decoding
NF_SET_ECC_DEC();
NF_MECC_Reset();
NF_MECC_UnLock();
nPosPtr = NAND_SCXT_OFFSET/4;
if (SECTORS_PER_PAGE == 4)
{
for (nCnt = 0; nCnt < (NAND_SECC_OFFSET-NAND_SCXT_OFFSET)/4; nCnt++)
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // 12 byte Spare Context(->aSpareData) + 32 byte Sector ECC data(->aMECC)
}
if (SECTORS_PER_PAGE == 8)
{
for (nCnt = 0; nCnt < (NAND_SECC_OFFSET_4K-NAND_SCXT_OFFSET)/4; nCnt++)
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // 20 byte Spare Context(->aSpareData) + 64 byte Sector ECC data(->aMECC)
}
NF_CE_H(nBank);
NF_SET_CLK(DUMMY_R_TACLS, DUMMY_R_TWRPH0, DUMMY_R_TWRPH1); // Don't set clk to (0, 0, 0) !!! Decoding error occurs
#if (NAND_TRANS_MODE == ASM)
if (SECTORS_PER_PAGE == 4)
{
_Write_Dummy_468Byte_AllFF();
}
else if (SECTORS_PER_PAGE == 8)
{
_Write_Dummy_428Byte_AllFF();
}
#elif (NAND_TRANS_MODE == DMA)
Write_Dummy_468Byte_AllFF_DMA();
#endif
//NF_MECC_Lock(); // Do NOT Lock MECC when using 4-bit ECC Decoding
NF_CLEAR_ECC_DEC_DONE();
if (bCheckMore == TRUE32)
{
NF_DATA_W4(pSpareCxt[(((SECTORS_PER_PAGE==4)?NAND_SECC2_OFFSET:NAND_SECC2_OFFSET_4K)/4)]); // Write 2nd Spare ECC, ->aSECC[2]
NF_DATA_W4(pSpareCxt[(((SECTORS_PER_PAGE==4)?NAND_SECC2_OFFSET:NAND_SECC2_OFFSET_4K)/4)+1]); // Actually after read 7th byte, ECC decoding starts!! ->aSECC[3]
bCheckMore = FALSE32;
}
else
{
NF_DATA_W4(pSpareCxt[(((SECTORS_PER_PAGE==4)?NAND_SECC_OFFSET:NAND_SECC_OFFSET_4K)/4)]); // Write modified ECC for the 53th bit on SECC data ->aSECC[0]
NF_DATA_W4((pSpareCxt[(((SECTORS_PER_PAGE==4)?NAND_SECC_OFFSET:NAND_SECC_OFFSET_4K)/4)])^(1<<19)); // position to be modified on SECC[1] ->aSECC[1]
bCheckMore = TRUE32;
}
NF_SET_CLK(DEFAULT_TACLS, DEFAULT_TWRPH0, DEFAULT_TWRPH1);
NF_CE_L(nBank);
// Wait Spare ECC Compare Done
NF_WAIT_ECC_DEC_DONE();
nRet = Decoding_SpareECC((UINT8 *)pSpareCxt[NAND_SCXT_OFFSET/4]); // ->aSpareData
if (bCheckMore == TRUE32)
goto _B_CheckMore;
}
}
else
{
// just read Spare ECC from NAND for read pointer, NOT decoding ECC
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // 8 byte Spare ECC data, ->aSECC[0]
pSpareCxt[nPosPtr++] = NF_DATA_R4();
pSpareCxt[nPosPtr++] = NF_DATA_R4(); // 8 byte Spare ECC data 2nd copy ->aSECC[2]
pSpareCxt[nPosPtr++] = NF_DATA_R4();
}
if (nRet&ECC_UNCORRECTABLE_ERROR)
{
NAND_ERR((_T("[FIL:ERR] Read_Spare() : ECC Uncorrectable Error in Spare of Page %d\r\n"), nPpn));
}
else if (nRet&ECC_CORRECTABLE_ERROR)
{
NAND_MSG((_T("[FIL] Read_Spare() : ECC Correctable Error in Spare of Page %d\r\n"), nPpn));
}
NAND_MSG((_T("[FIL]--Read_Spare()\r\n")));
return nRet;
}
PRIVATE VOID
Write_Sector(UINT32 nPpn, UINT32 nSctOffset, UINT8* pBuf)
{
UINT32 nOffset;
#if ECC_MODULE_TEST_SIMULATION
BOOL32 bChangeData = FALSE;
#endif
NAND_MSG((_T("[FIL]++Write_Sector(%d, %d)\r\n"), nPpn, nSctOffset));
#if ECC_MODULE_TEST_SIMULATION
Loop1:
#endif
nOffset = NAND_SECTOR_SIZE*nSctOffset;
NF_CMD(CMD_RANDOM_DATA_INPUT);
NF_ADDR(nOffset&0xFF);
NF_ADDR((nOffset>>8)&0xFF);
#if ECC_MODULE_TEST_SIMULATION
if (IS_CHECK_SPARE_ECC == TRUE32 && bChangeData == FALSE)
#else
if (IS_CHECK_SPARE_ECC == TRUE32)
#endif
{
// Initialize 4-bit ECC Encoding
NF_SET_ECC_ENC();
NF_MECC_Reset();
NF_CLEAR_ECC_ENC_DONE();
NF_MECC_UnLock();
}
#if ECC_MODULE_TEST_SIMULATION
else if (bChangeData == TRUE)
{
if (nSctOffset == 0) // forcefully happen to error on 4-bit in case of ECC mobule error
{
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+243) ^= (1<<4);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+419) ^= (1<<3);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+333) ^= (1<<2);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+308) ^= (1<<4);
}
else if (nSctOffset == 1) // forcefully happen to error on 4-bit in case of ECC mobule error
{
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+228) ^= (1<<0);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+400) ^= (1<<3);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+486) ^= (1<<4);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+165) ^= (1<<2);
}
else if (nSctOffset == 2) // forcefully happen to error on 4-bit except ECC mobule error
{
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+228) ^= (1<<0);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+400) ^= (1<<3);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+486) ^= (1<<4);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+165) ^= (1<<1);
}
else if (nSctOffset == 3) // forcefully happen to error on 3-bit in case of ECC mobule error
{
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+148) ^= (1<<3);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+435) ^= (1<<2);
*(pBuf+NAND_SECTOR_SIZE*nSctOffset+501) ^= (1<<1);
}
}
#endif
#if (NAND_TRANS_MODE == ASM)
if ((UINT32)pBuf&0x3)
{
_Write_512Byte_Unaligned(pBuf+NAND_SECTOR_SIZE*nSctOffset);
}
else
{
_Write_512Byte(pBuf+NAND_SECTOR_SIZE*nSctOffset);
}
#elif (NAND_TRANS_MODE == DMA)
Write_512Byte_DMA(pBuf+NAND_SECTOR_SIZE*nSctOffset);
#endif
#if ECC_MODULE_TEST_SIMULATION
if (IS_CHECK_SPARE_ECC == TRUE32 && bChangeData == FALSE)
#else
if (IS_CHECK_SPARE_ECC == TRUE32)
#endif
{
NF_MECC_Lock();
// Waiting for Main ECC Encoding
NF_WAIT_ECC_ENC_DONE();
}
#if ECC_MODULE_TEST_SIMULATION
if (bChangeData == FALSE)
{
bChangeData = TRUE;
goto Loop1;
}
#endif
NAND_MSG((_T("[FIL]--Write_Sector()\r\n")));
return;
}
PRIVATE VOID
Write_Spare(UINT32 nBank, UINT32 nPpn, pSECCCxt pSpareCxt)
{
UINT32 nOffset;
NAND_MSG((_T("[FIL]++Write_Spare(%d, %d)\r\n"), nBank, nPpn));
nOffset = BYTES_PER_MAIN_PAGE;
NF_CMD(CMD_RANDOM_DATA_INPUT);
NF_ADDR(nOffset&0xFF);
NF_ADDR((nOffset>>8)&0xFF);
NF_DATA_W(pSpareCxt->cBadMark); // 1 byte Bad Mark
NF_DATA_W(pSpareCxt->cCleanMark); // 1 byte Clean Mark
#if 1
NF_DATA_W(0xff); // 2 byte Reserved
NF_DATA_W(0xff);
#else
NF_DATA_W(pSpareCxt->cReserved[0]); // 2 byte Reserved
NF_DATA_W(pSpareCxt->cReserved[1]);
#endif
if (IS_CHECK_SPARE_ECC == TRUE32)
{
// Initialize 4-bit ECC Encoding
NF_SET_ECC_ENC();
NF_MECC_Reset();
NF_CLEAR_ECC_ENC_DONE();
NF_MECC_UnLock();
}
if (SECTORS_PER_PAGE == 4)
{
NF_DATA_W4(pSpareCxt->aSpareData[0]); // 12 byte Spare Context
NF_DATA_W4(pSpareCxt->aSpareData[1]);
NF_DATA_W4(pSpareCxt->aSpareData[2]);
NF_DATA_W4(pSpareCxt->aMECC[0]); // 8 byte Sector0 ECC data
NF_DATA_W4(pSpareCxt->aMECC[1]);
NF_DATA_W4(pSpareCxt->aMECC[2]); // 8 byte Sector1 ECC data
NF_DATA_W4(pSpareCxt->aMECC[3]);
NF_DATA_W4(pSpareCxt->aMECC[4]); // 8 byte Sector2 ECC data
NF_DATA_W4(pSpareCxt->aMECC[5]);
NF_DATA_W4(pSpareCxt->aMECC[6]); // 8 byte Sector3 ECC data
NF_DATA_W4(pSpareCxt->aMECC[7]);
}
else if (SECTORS_PER_PAGE == 8)
{
NF_DATA_W4(pSpareCxt->aSpareData[0]); // 20 byte Spare Context for 4KByte/Page
NF_DATA_W4(pSpareCxt->aSpareData[1]);
NF_DATA_W4(pSpareCxt->aSpareData[2]);
NF_DATA_W4(pSpareCxt->aSpareData[3]);
NF_DATA_W4(pSpareCxt->aSpareData[4]);
NF_DATA_W4(pSpareCxt->aMECC[0]); // 8 byte Sector0 ECC data
NF_DATA_W4(pSpareCxt->aMECC[1]);
NF_DATA_W4(pSpareCxt->aMECC[2]); // 8 byte Sector1 ECC data
NF_DATA_W4(pSpareCxt->aMECC[3]);
NF_DATA_W4(pSpareCxt->aMECC[4]); // 8 byte Sector2 ECC data
NF_DATA_W4(pSpareCxt->aMECC[5]);
NF_DATA_W4(pSpareCxt->aMECC[6]); // 8 byte Sector3 ECC data
NF_DATA_W4(pSpareCxt->aMECC[7]);
NF_DATA_W4(pSpareCxt->aMECC[8]); // 8 byte Sector4 ECC data
NF_DATA_W4(pSpareCxt->aMECC[9]);
NF_DATA_W4(pSpareCxt->aMECC[10]); // 8 byte Sector5 ECC data
NF_DATA_W4(pSpareCxt->aMECC[11]);
NF_DATA_W4(pSpareCxt->aMECC[12]); // 8 byte Sector6 ECC data
NF_DATA_W4(pSpareCxt->aMECC[13]);
NF_DATA_W4(pSpareCxt->aMECC[14]); // 8 byte Sector7 ECC data
NF_DATA_W4(pSpareCxt->aMECC[15]);
}
else
{
WMR_ASSERT(FALSE32);
}
if (IS_CHECK_SPARE_ECC == TRUE32)
{
// Write Dummy 500 byte for ECC Encoding using CE Don't care
NF_CE_H(nBank);
NF_SET_CLK(DUMMY_W_TACLS, DUMMY_W_TWRPH0, DUMMY_W_TWRPH1); // Don't set clk to (0, 0, 0) !!! Decoding error occurs
#if (NAND_TRANS_MODE == ASM)
if (SECTORS_PER_PAGE == 4)
{
_Write_Dummy_468Byte_AllFF();
}
else if (SECTORS_PER_PAGE == 8)
{
_Write_Dummy_428Byte_AllFF();
}
#elif (NAND_TRANS_MODE == DMA)
Write_Dummy_468Byte_AllFF_DMA();
#endif
NF_SET_CLK(DEFAULT_TACLS, DEFAULT_TWRPH0, DEFAULT_TWRPH1);
NF_CE_L(nBank);
NF_MECC_Lock();
// Waiting for Main ECC Encoding
NF_WAIT_ECC_ENC_DONE();
pSpareCxt->aSECC[0] = NF_MECC0(); // Spare ECC x 2 copies
pSpareCxt->aSECC[1] = NF_MECC1();
pSpareCxt->aSECC[2] = NF_MECC0();
pSpareCxt->aSECC[3] = NF_MECC1();
}
NF_DATA_W4(pSpareCxt->aSECC[0]); // Spare ECC 8 bytes
NF_DATA_W4(pSpareCxt->aSECC[1]);
NF_DATA_W4(pSpareCxt->aSECC[2]); // Spare ECC 8 bytes 2nd copy
NF_DATA_W4(pSpareCxt->aSECC[3]);
NAND_MSG((_T("[FIL]--Write_Spare()\r\n")));
return;
}
#define NUMBER_OF_ECC_ERROR 3
PRIVATE UINT32
Decoding_MainECC(UINT8* pBuf)
{
UINT32 nError0, nError1;
UINT32 nErrorCnt, nErrorByte, nErrorPattern;
UINT32 nRet = 0;
UINT8 nErrorBitPat;
NAND_MSG((_T("[FIL]++Decoding_MainECC()\r\n")));
nError0 = NF_ECC_ERR0();
nError1 = NF_ECC_ERR1();
nErrorCnt = (nError0>>26)&0x7;
if (nErrorCnt == 0) // No Error
{
NAND_MSG((_T("[FIL] Decoding_MainECC() : No ECC Error\r\n")));
}
else if (nErrorCnt > 4) // Uncorrectable Error
{
NAND_ERR((_T("[FIL:ERR] Decoding_MainECC() : Uncorrectable Error\r\n")));
nRet = ECC_UNCORRECTABLE_ERROR;
}
else // Correctable Error
{
NAND_MSG((_T("[FIL] Decoding_MainECC() : Correctable Error %d bit\r\n"), nErrorCnt));
nErrorPattern = NF_ECC_ERR_PATTERN();
// 1st Bit Error Correction
nErrorByte = nError0&0x3ff;
nErrorBitPat = (UINT8)(nErrorPattern&0xff⌨️ 快捷键说明
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