uart_testbench.v

uart协议、实现、验证

            if (~lsr_reg_bit6_change_allowed)
            begin
              `BENCH_ERROR("Bit 6 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end
    // Bit 7 - Error in RX FIFO
    initial
    begin
      lsr_reg_bit7_change_allowed = 0;
      @(reset_released);
      #10;
      fork
      begin: error_changing
        forever
        begin
          if ((rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0))
          begin
            wait (rx_parity_err || rx_framing_err || rx_framing_glitch || rx_break_int);
            lsr_reg_bit7_change_allowed = 1'b1;
            repeat (3) @(posedge wb_clk);
            #2;
            lsr_reg_bit7_change_allowed = 0;
            // check bit
            if (~lsr_reg[7])
            begin
              `BENCH_ERROR("Bit 7 of LSR register not '1'!");
              -> error_detected;
            end
          end
          else
          begin
            wait (lsr_reg_read && (rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0));
            lsr_reg_bit7_change_allowed = 1'b1;
            repeat (2) @(posedge wb_clk);
            #2;
            lsr_reg_bit7_change_allowed = 0;
            // check bit
            if (lsr_reg[7])
            begin
              `BENCH_ERROR("Bit 7 of LSR register not '0'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit7_changing
        forever
        begin
          wait (~lsr_reg_bit7_change_allowed);
          begin
            @(lsr_reg[7] or lsr_reg_bit7_change_allowed);
            if (~lsr_reg_bit7_change_allowed)
            begin
              `BENCH_ERROR("Bit 7 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end


// UART transmitter monitor
//#########################

  // TX FIFO status
  always@(tx_fifo_wr_pointer or tx_fifo_rd_pointer)
  begin
    if (tx_fifo_wr_pointer >= tx_fifo_rd_pointer)
      tx_fifo_status = tx_fifo_wr_pointer - tx_fifo_rd_pointer;
    else
      tx_fifo_status = (5'h1F - tx_fifo_rd_pointer) + tx_fifo_wr_pointer;
  end
  // TX FIFO and TX data
  initial
  begin
    tx_fifo_wr_pointer = 0;
    tx_fifo_rd_pointer = 0;
    tx_shift_reg_empty = 1;
    tx_fifo_status     = 0;
    tx_start_bit_edge  = 1;
    fork
    begin:write_tx_shift_reg_read_tx_fifo
      forever
      begin
        wait ((tx_fifo_status !== 0) && tx_shift_reg_empty && tx_start_bit_edge && ~stx_pad_o);
        tx_start_bit_edge  = 0;
        tx_shift_reg = tx_fifo[tx_fifo_rd_pointer];
        tx_shift_reg_empty = 0;
        @(testbench.i_uart_device.device_received_last_bit);
        repeat (16393) @(posedge wb_clk);
        tx_fifo_rd_pointer = tx_fifo_rd_pointer + 1'b1;
        @(posedge wb_clk);
        if (tx_fifo_status == 0)
        begin
          `BENCH_MSG("TX FIFO is empty!");
        end
      end
    end
    begin:write_tx_fifo
      forever
      begin
        @(tx_reg_written); // write to FIFO
        repeat (1) @(posedge wb_clk); // delay when writing into registers
        if (tx_fifo_status <= 5'h0F)
        begin
          tx_fifo[tx_fifo_wr_pointer] = reg_dat;
          tx_fifo_wr_pointer = tx_fifo_wr_pointer + 1'b1;
        end
        else // FIFO overflow
        begin
          `BENCH_WARNING("TX FIFO overflow!");
        end
      end
    end
    begin:empty_tx_fifo
      forever
      begin
        wait (fcr_reg[2]);
        tx_fifo_wr_pointer = 0;
        tx_fifo_rd_pointer = 0;
        @(posedge wb_clk);
        if (tx_fifo_status == 0)
        begin
          `BENCH_MSG("TX FIFO is empty!");
        end
      end
    end
    begin:read_tx_shift_reg
      forever
      begin
        @(testbench.i_uart_device.device_received_packet);
        // Check data
        if (tx_shift_reg != testbench.i_uart_device.rx_data)
        begin
          `BENCH_ERROR("TX data has ERROR!");
          -> error_detected;
        end
        else
          `BENCH_MSG("TX data correct!");
        if (testbench.i_uart_device.rx_parity_error)
        begin
          `BENCH_ERROR("TX data has parity ERROR!");
          -> error_detected;
        end
        else
          `BENCH_MSG("TX data parity correct!");
        if (testbench.i_uart_device.rx_framing_error)
        begin
          `BENCH_ERROR("TX data has framing ERROR!");
          -> error_detected;
        end
        else
          `BENCH_MSG("TX data framing correct!");
        // Set TX FIFO read pointer
        tx_start_bit_edge  = 1;
        repeat (7) @(wb_clk);
        if (tx_shift_reg_empty == 0)
        begin
          tx_shift_reg_empty = 1'b1;
        end
        else
        begin
          `BENCH_ERROR("TX shift register empty while transmiting data!");
          -> error_detected;
        end
      end
    end
    join
  end


// UART receiver monitor
//######################

  // RX FIFO status
  always@(rx_fifo_wr_pointer or rx_fifo_rd_pointer)
  begin
    if (rx_fifo_wr_pointer >= rx_fifo_rd_pointer)
      rx_fifo_status = rx_fifo_wr_pointer - rx_fifo_rd_pointer;
    else
      rx_fifo_status = (5'h1F - rx_fifo_rd_pointer) + rx_fifo_wr_pointer;
  end
  // RX FIFO and RX data
  initial
  begin
    rx_parity_err      = 0;
    rx_framing_err     = 0;
    rx_framing_glitch  = 0;
    rx_break_int       = 0;
    rx_overrun_err_occured = 0;
    rx_fifo_par        = 0;
    rx_fifo_frm        = 0;
    rx_fifo_brk        = 0;
    rx_shift_reg_full  = 0;
    rx_fifo_wr_pointer = 0;
    rx_fifo_rd_pointer = 0;
    rx_fifo_status     = 0;
    fork
    begin:write_rx_shift_reg
      forever
      begin
        @(testbench.i_uart_device.device_sent_packet);
        repeat (1) @(posedge wb_clk);
        rx_shift_reg   = testbench.i_uart_device.sent_data;
        rx_parity_err  = testbench.i_uart_device.tx_parity_enabled && 
                         (testbench.i_uart_device.tx_parity_wrong || 
                          (  // sample point is BIT_NUM * 2 - 1 => 3, 5, 7...
                           ((testbench.i_uart_device.tx_glitch_num == (3 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (5 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (7 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (9 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (11 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (13 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (15 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (17 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (19 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (21 * 8 * testbench.i_uart_device.T_divisor)) ||
                            (testbench.i_uart_device.tx_glitch_num == (23 * 8 * testbench.i_uart_device.T_divisor))) &&
                           (testbench.i_uart_device.tx_glitch_num[23:0] < ((testbench.i_uart_device.tx_length + 2'h1) *
                             16 * testbench.i_uart_device.T_divisor))
                         ));
        rx_framing_err = testbench.i_uart_device.tx_framing_wrong;
        rx_framing_glitch = (testbench.i_uart_device.tx_glitch_num == ((((testbench.i_uart_device.tx_length + 2'h2 +
                               testbench.i_uart_device.tx_parity_enabled) * 
                                2) - 1'b1) * 8 * testbench.i_uart_device.T_divisor));
        rx_break_int   = testbench.i_uart_device.tx_break_enable && 
                         (testbench.i_uart_device.tx_break_num[15:0] >= ((testbench.i_uart_device.tx_length + 2'h2 +
                            testbench.i_uart_device.tx_parity_enabled) * 
                           16 * testbench.i_uart_device.T_divisor));
        -> testbench.i_uart_device.sent_packet_received;
        if (rx_fifo_status > 5'h0F)
          rx_overrun_err_occured = 1'b1;
        rx_shift_reg_full = 1'b1;
      end
    end
    begin:write_rx_fifo_read_rx_shift_reg
      forever
      begin
        wait (rx_shift_reg_full);
        if (rx_fifo_status <= 5'h0F)
        begin
          rx_fifo_data[rx_fifo_wr_pointer] = testbench.i_uart_device.sent_data;
          rx_fifo_par[rx_fifo_wr_pointer]  = rx_parity_err; 
          rx_fifo_frm[rx_fifo_wr_pointer]  = rx_framing_err || rx_framing_glitch; 
          rx_fifo_brk[rx_fifo_wr_pointer]  = rx_break_int; 
          rx_fifo_wr_pointer = rx_fifo_wr_pointer + 1'b1;
        end
        else // FIFO overflow
        begin
          `BENCH_WARNING("RX FIFO overflow!");
        end
        repeat (1) @(posedge wb_clk);
        rx_shift_reg_full = 0;
      end
    end
    begin:empty_rx_fifo
      forever
      begin
        wait (fcr_reg[1]);
        rx_fifo_wr_pointer = 0;
        rx_fifo_rd_pointer = 0;
//        rx_fifo_par        = 0;
//        rx_fifo_frm        = 0;
//        rx_fifo_brk        = 0;
        @(posedge wb_clk);
        if (rx_fifo_status == 0)
        begin
          `BENCH_MSG("RX FIFO is empty!");
        end
      end
    end
    begin:read_rx_fifo
      rx_fifo_read = 0;
      forever
      begin
        @(rx_reg_read);
        if (rx_fifo_status > 0)
        begin
          rx_fifo_read = 1'b1;
          // Check data
          if (rx_fifo_data[rx_fifo_rd_pointer] != reg_dat)
          begin
            `BENCH_ERROR("RX data has ERROR!");
            -> error_detected;
          end
          else
          begin
            `BENCH_MSG("RX data correct!");
          end
          // Set RX FIFO read pointer
          repeat (1) @(posedge wb_clk);
          rx_fifo_read = 0;
          rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
        end
        else
        begin
          `BENCH_WARNING("Reading RX FIFO while RX FIFO is empty!");
        end


        if ((~rx_fifo_frm[rx_fifo_rd_pointer] && lsr_reg[3]) ||
            (rx_fifo_frm[rx_fifo_rd_pointer] && ~lsr_reg[3]))
        begin
          `BENCH_ERROR("RX data has wrong framing ERROR!");
          -> error_detected;
        end
        else
          `BENCH_MSG("RX data has correct framing error!");
        // Set RX FIFO read pointer
        repeat (1) @(posedge wb_clk);
        rx_fifo_read = 0;
        if (rx_fifo_status > 0)
        begin
//          rx_fifo_par[rx_fifo_rd_pointer] = 1'b0; 
//          rx_fifo_frm[rx_fifo_rd_pointer] = 1'b0; 
//          rx_fifo_brk[rx_fifo_rd_pointer] = 1'b0; 
          rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
        end
      end
    end
    join
  end


// UART interrupt monitor
//#######################




endmodule