uart_testbench.v

uart协议、实现、验证

            // check bit
            if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
            begin
              `BENCH_ERROR("Bit 2 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
            begin
              `BENCH_ERROR("Bit 2 of LSR register not '0'!");
              -> error_detected;
            end
          end
          else
          begin
            wait (lsr_reg_read);
            lsr_reg_bit2_change_allowed = 1'b1;
            repeat (1) @(posedge wb_clk);
            #2;
            lsr_reg_bit2_change_allowed = 0;
            if (rx_fifo_par_rd_pointer < rx_fifo_rd_pointer)
            begin
              for (i2 = rx_fifo_par_rd_pointer; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
                rx_fifo_par[i2] = 0;
              rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
            end
            else if (rx_fifo_par_rd_pointer > rx_fifo_rd_pointer)
            begin
              for (i2 = rx_fifo_par_rd_pointer; i2 <= 31; i2 = i2 + 1)
                rx_fifo_par[i2] = 0;
              for (i2 = 0; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
                rx_fifo_par[i2] = 0;
              rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
            end
            else
            begin
              rx_fifo_par = 0;
              rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
            end
            // check bit
            if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
            begin
              `BENCH_ERROR("Bit 2 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
            begin
              `BENCH_ERROR("Bit 2 of LSR register not '0'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit2_changing
        forever
        begin
          wait (~lsr_reg_bit2_change_allowed);
          begin
            @(lsr_reg[2] or lsr_reg_bit2_change_allowed);
            if (~lsr_reg_bit2_change_allowed)
            begin
              `BENCH_ERROR("Bit 2 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end
    // Bit 3 - Framing Error
    initial
    begin
      lsr_reg_bit3_change_allowed = 0;
      rx_fifo_frm_rd_pointer      = 0;
      @(reset_released);
      #10;
      fork
      begin: rx_framing_err_changing
        forever
        begin
          if (~rx_fifo_frm[rx_fifo_frm_rd_pointer])
          begin
            wait (rx_fifo_read);
            lsr_reg_bit3_change_allowed = 1'b1;
            repeat (1) @(posedge wb_clk);
            #2;
            lsr_reg_bit3_change_allowed = 0;
            rx_fifo_frm_rd_pointer = rx_fifo_frm_rd_pointer + 1'b1;
            // check bit
            if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
            begin
              `BENCH_ERROR("Bit 3 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
            begin
              `BENCH_ERROR("Bit 3 of LSR register not '0'!");
              -> error_detected;
            end
          end
          else
          begin
            wait (lsr_reg_read);
            lsr_reg_bit3_change_allowed = 1'b1;
            repeat (1) @(posedge wb_clk);
            #2;
            lsr_reg_bit3_change_allowed = 0;
            if (rx_fifo_frm_rd_pointer < rx_fifo_rd_pointer)
            begin
              for (i3 = rx_fifo_frm_rd_pointer; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
                rx_fifo_frm[i3] = 0;
              rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
            end
            else if (rx_fifo_frm_rd_pointer > rx_fifo_rd_pointer)
            begin
              for (i3 = rx_fifo_frm_rd_pointer; i3 <= 31; i3 = i3 + 1)
                rx_fifo_frm[i3] = 0;
              for (i3 = 0; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
                rx_fifo_frm[i3] = 0;
              rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
            end
            else
            begin
              rx_fifo_frm = 0;
              rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
            end
            // check bit
            if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
            begin
              `BENCH_ERROR("Bit 3 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
            begin
              `BENCH_ERROR("Bit 3 of LSR register not '0'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit3_changing
        forever
        begin
          wait (~lsr_reg_bit3_change_allowed);
          begin
            @(lsr_reg[3] or lsr_reg_bit3_change_allowed);
            if (~lsr_reg_bit3_change_allowed)
            begin
              `BENCH_ERROR("Bit 3 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end
    // Bit 4 - Break Interrupt
    initial
    begin
      lsr_reg_bit4_change_allowed = 0;
      rx_fifo_brk_rd_pointer      = 0;
      @(reset_released);
      #10;
      fork
      begin: rx_break_int_changing
        forever
        begin
          if (~rx_fifo_brk[rx_fifo_brk_rd_pointer])
          begin
            wait (rx_fifo_read);
            lsr_reg_bit4_change_allowed = 1'b1;
            repeat (1) @(posedge wb_clk);
            #2;
            lsr_reg_bit4_change_allowed = 0;
            rx_fifo_brk_rd_pointer = rx_fifo_brk_rd_pointer + 1'b1;
            // check bit
            if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
            begin
              `BENCH_ERROR("Bit 4 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
            begin
              `BENCH_ERROR("Bit 4 of LSR register not '0'!");
              -> error_detected;
            end
          end
          else
          begin
            wait (lsr_reg_read);
            lsr_reg_bit4_change_allowed = 1'b1;
            repeat (1) @(posedge wb_clk);
            #2;
            lsr_reg_bit4_change_allowed = 0;
            if (rx_fifo_brk_rd_pointer < rx_fifo_rd_pointer)
            begin
              for (i4 = rx_fifo_brk_rd_pointer; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
                rx_fifo_brk[i4] = 0;
              rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
            end
            else if (rx_fifo_brk_rd_pointer > rx_fifo_rd_pointer)
            begin
              for (i4 = rx_fifo_brk_rd_pointer; i4 <= 31; i4 = i4 + 1)
                rx_fifo_brk[i4] = 0;
              for (i4 = 0; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
                rx_fifo_brk[i4] = 0;
              rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
            end
            else
            begin
              rx_fifo_brk = 0;
              rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
            end
            // check bit
            if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
            begin
              `BENCH_ERROR("Bit 4 of LSR register not '1'!");
              -> error_detected;
            end
            else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
            begin
              `BENCH_ERROR("Bit 4 of LSR register not '0'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit4_changing
        forever
        begin
          wait (~lsr_reg_bit4_change_allowed);
          begin
            @(lsr_reg[4] or lsr_reg_bit4_change_allowed);
            if (~lsr_reg_bit4_change_allowed)
            begin
              `BENCH_ERROR("Bit 4 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end
    // Bit 5 - Transmitter Holding Register Empty
    initial
    begin
      lsr_reg_bit5_change_allowed = 0;
      @(reset_released);
      #10;
      fork
      begin: tx_fifo_status_changing
        forever
        begin
          if (tx_fifo_status == 0)
          begin
//            @(tx_reg_written);
            wait (tx_fifo_status > 0);
            lsr_reg_bit5_change_allowed = 1'b1;
            repeat (3) @(posedge wb_clk);
            #2;
            lsr_reg_bit5_change_allowed = 0;
            if (lsr_reg[5])
            begin
              `BENCH_ERROR("Bit 5 of LSR register not '0'!");
              -> error_detected;
            end
          end
          else
          begin
            wait (tx_fifo_status == 0);
            lsr_reg_bit5_change_allowed = 1'b1;
            repeat (3) @(posedge wb_clk);
            #2;
            lsr_reg_bit5_change_allowed = 0;
            if (~lsr_reg[5])
            begin
              `BENCH_ERROR("Bit 5 of LSR register not '1'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit5_changing
        forever
        begin
          wait (~lsr_reg_bit5_change_allowed);
          begin
            @(lsr_reg[5] or lsr_reg_bit5_change_allowed);
            if (~lsr_reg_bit5_change_allowed)
            begin
              `BENCH_ERROR("Bit 5 of LSR register should not change!");
              -> error_detected;
            end
          end
        end
      end
      join
    end
    // Bit 6 - Transmitter Empty
    initial
    begin
      lsr_reg_bit6_change_allowed = 0;
      @(reset_released);
      #10;
      fork
      begin: tx_fifo_status_and_shift_reg_changing
        forever
        begin
          if ((tx_fifo_status == 0) && tx_shift_reg_empty)
          begin
//            @(tx_reg_written);
            wait (tx_fifo_status > 0);
            lsr_reg_bit6_change_allowed = 1'b1;
            repeat (3) @(posedge wb_clk);
            #2;
            lsr_reg_bit6_change_allowed = 0;
            if (lsr_reg[6])
            begin
              `BENCH_ERROR("Bit 6 of LSR register not '0'!");
              -> error_detected;
            end
          end
          else
          begin
            wait ((tx_fifo_status == 0) && tx_shift_reg_empty);
            lsr_reg_bit6_change_allowed = 1'b1;
            repeat (3) @(posedge wb_clk);
            #2;
            lsr_reg_bit6_change_allowed = 0;
            if (~lsr_reg[6])
            begin
              `BENCH_ERROR("Bit 6 of LSR register not '1'!");
              -> error_detected;
            end
          end
        end
      end
      begin: lsr_reg_bit6_changing
        forever
        begin
          wait (~lsr_reg_bit6_change_allowed);
          begin
            @(lsr_reg[6] or lsr_reg_bit6_change_allowed);