uart_testbench.v

uart协议、实现、验证

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_testbench.v                                            ////
////                                                              ////
////  This file is part of the "uart16550" project                ////
////  http://www.opencores.org/projects/uart16550/                ////
////                                                              ////
////  Author(s):                                                  ////
////      - [e-mail] (Tadej Markovic)                  ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_testbench.v,v $
// Revision 1.1  2004/03/27 03:55:17  tadejm
// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.
//
//
//


`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
`include "timescale.v"

module testbench;


parameter max_wait_cnt = 20000;

// INTERNAL signals
//#################

  // WB slave signals
  //#################

    // UART Wishbone Slave signals
    wire                         wb_int_o;
    wire [`UART_ADDR_WIDTH-1:0]  wbs_adr_i;
    wire [`UART_DATA_WIDTH-1:0]  wbs_dat_i;
    wire [`UART_DATA_WIDTH-1:0]  wbs_dat_o;
    wire                  [3:0]  wbs_sel_i;
    wire                         wbs_cyc_i;
    wire                         wbs_stb_i;
    wire                  [2:0]  wbs_cti_i;
    wire                  [1:0]  wbs_bte_i;
    wire                         wbs_we_i;
    wire                         wbs_ack_o;
    wire                         wbs_rty_o = 1'b0;
    wire                         wbs_err_o = 1'b0;

  // UART signals
  //#############

    // UART Serial Data I/O signals
    wire                         stx_pad_o;
    wire                         srx_pad_i;
    // UART Modem I/O signals
    wire                         rts_pad_o;
    wire                         cts_pad_i;
    wire                         dtr_pad_o;
    wire                         dsr_pad_i;
    wire                         ri_pad_i;
    wire                         dcd_pad_i;
  `ifdef UART_HAS_BAUDRATE_OUTPUT
    wire                         baud_o;
  `endif

  // System signals
  //###############

    // WB clock signal
    reg          wb_clk; // divided device clock with period T_wb_clk_period
    // WB clock enable signal
    reg          wb_clk_en = 1'b1;
    // WB clock period variable
    real         T_wb_clk_period = 20;
    // WB reset signal
    reg          wb_reset;
    event        reset_aserted;
    event        reset_released;
    event        int_aserted;
    event        int_released;
    // Error detection event
    event        error_detected;

  // UART register monitor
  //#########################

    // Line Status Register
      // Reading LSR register
      reg          lsr_reg_read;
      // Bit 0 - Data Ready
      reg          lsr_reg_bit0_change_allowed;
      // Bit 1 - Overrun Error
      reg          lsr_reg_bit1_change_allowed;
      // Bit 2 - Parity Error
      reg          lsr_reg_bit2_change_allowed;
      reg   [4:0]  rx_fifo_par_rd_pointer;
      integer      i2;
      // Bit 3 - Framing Error
      reg          lsr_reg_bit3_change_allowed;
      reg   [4:0]  rx_fifo_frm_rd_pointer;
      integer      i3;
      // Bit 4 - Break Interrupt
      reg          lsr_reg_bit4_change_allowed;
      reg   [4:0]  rx_fifo_brk_rd_pointer;
      integer      i4;
      // Bit 5 - Transmitter Holding Register Empty
      reg          lsr_reg_bit5_change_allowed;
      // Bit 6 - Transmitter Empty
      reg          lsr_reg_bit6_change_allowed;
      // Bit 7 - Error in RX FIFO
      reg          lsr_reg_bit7_change_allowed;

  // UART transmitter monitor
  //#########################

    // TX FIFO signals
    reg   [7:0]  tx_shift_reg;
    reg          tx_shift_reg_empty;
    reg          tx_start_bit_edge;
    reg   [7:0]  tx_fifo [0:31]; 
    reg   [4:0]  tx_fifo_wr_pointer;
    reg   [4:0]  tx_fifo_rd_pointer;
    reg   [4:0]  tx_fifo_status;

  // UART receiver monitor
  //######################

    // RX FIFO signals
    reg   [7:0]  rx_shift_reg;
    reg          rx_shift_reg_full;
    reg          rx_parity_err;
    reg          rx_framing_err;
    reg          rx_framing_glitch;
    reg          rx_break_int;
    reg          rx_overrun_err_occured;
    reg   [7:0]  rx_fifo_data [0:31]; 
    reg  [31:0]  rx_fifo_par; 
    reg  [31:0]  rx_fifo_frm; 
    reg  [31:0]  rx_fifo_brk; 
    reg   [4:0]  rx_fifo_wr_pointer;
    reg   [4:0]  rx_fifo_rd_pointer;
    reg   [4:0]  rx_fifo_status;
    reg          rx_fifo_read;

  // UART register tracker
  //######################

    // Registers
    wire  [7:0]  ier_reg;
    wire  [7:0]  iir_reg;
    wire  [7:0]  fcr_reg;
    wire  [7:0]  lcr_reg;
    wire  [7:0]  mcr_reg;
    wire  [7:0]  lsr_reg;
    wire  [7:0]  msr_reg;
    wire  [7:0]  dll_reg;
    wire  [7:0]  dlm_reg;
    // Events
    event        ier_reg_changed;
    event        iir_reg_changed;
    event        fcr_reg_changed;
    event        lcr_reg_changed;
    event        mcr_reg_changed;
    event        lsr_reg_changed;
    event        msr_reg_changed;
    event        dll_reg_changed;
    event        dlm_reg_changed;
    // Register access
    reg   [`UART_ADDR_WIDTH-1:0] reg_adr;
    reg   [`UART_DATA_WIDTH-1:0] reg_dat;
    reg          reg_dlab;
    event        reg_written;
    event        tx_reg_written;
    event        reg_read;
    event        rx_reg_read;



uart_top                #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH) i_uart_top
(
    .wb_clk_i           (wb_clk),
    .wb_rst_i           (wb_reset),
    .int_o              (wb_int_o),
// WB slave signals - 2 address locations for two registers!
    .wb_cyc_i           (wbs_cyc_i),
    .wb_stb_i           (wbs_stb_i),
    .wb_we_i            (wbs_we_i),
    .wb_sel_i           (wbs_sel_i),
    .wb_adr_i           (wbs_adr_i),
    .wb_dat_i           (wbs_dat_i),
    .wb_dat_o           (wbs_dat_o),
    .wb_ack_o           (wbs_ack_o),
// UART signals
    .stx_pad_o          (stx_pad_o),
    .srx_pad_i          (srx_pad_i),
// Modem signals
    .rts_pad_o          (rts_pad_o),
    .cts_pad_i          (cts_pad_i),
    .dtr_pad_o          (dtr_pad_o),
    .dsr_pad_i          (dsr_pad_i),
    .ri_pad_i           (ri_pad_i),
    .dcd_pad_i          (dcd_pad_i)
`ifdef UART_HAS_BAUDRATE_OUTPUT
    ,
    .baud_o             (baud_o)
`endif
); 

uart_device             i_uart_device
(
// UART signals
    .stx_i              (stx_pad_o),
    .srx_o              (srx_pad_i),
// Modem signals    
    .rts_i              (rts_pad_o),
    .cts_o              (cts_pad_i),
    .dtr_i              (dtr_pad_o),
    .dsr_o              (dsr_pad_i),
    .ri_o               (ri_pad_i),
    .dcd_o              (dcd_pad_i)
);

wb_master_model         #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH, 4) i_wb_master_model
(
    .wb_rst_i           (wb_reset),
    .wb_clk_i           (wb_clk),
    .wbm_cyc_o          (wbs_cyc_i),
    .wbm_cti_o          (),
    .wbm_bte_o          (),
    .wbm_stb_o          (wbs_stb_i),
    .wbm_we_o           (wbs_we_i),
    .wbm_adr_o          (wbs_adr_i),
    .wbm_sel_o          (wbs_sel_i),
    .wbm_dat_o          (wbs_dat_i),
    .wbm_dat_i          (wbs_dat_o),
    .wbm_ack_i          (wbs_ack_o),
    .wbm_err_i          (wbs_err_o), // inactive (1'b0)
    .wbm_rty_i          (wbs_rty_o)  // inactive (1'b0)
);


initial
begin:system
  // Initial system values
  wb_reset = 1'b1;
  wb_clk = 1'b0;
end


// WB clock generation (DEVICE clock is generated in uart_device.v)
//#################################################################

  // DEVICE's clock generation: 
  //    ----------------
  //    // rx_clk rising edge
  //    always@(posedge rx_clk)
  //      if (rx_clk_en)
  //        #(T_clk_period / 2) rx_clk = 1'b0;
  //    // rx_clk falling edge
  //    always@(negedge rx_clk)
  //      if (rx_clk_en)
  //        #(T_clk_period / 2) rx_clk = 1'b1;
  //    ----------------
  // DEVICE's transmit clocks generation: 
  //    ----------------
  //    // tx_clk rising edge
  //    always@(posedge tx_clk)
  //      if (tx_clk_en)
  //        #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b0;
  //    // tx_clk falling edge
  //    always@(negedge tx_clk)
  //      if (tx_clk_en)
  //        #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b1;
  //    ----------------

  // WB clock
  always@(posedge wb_clk)
    if (wb_clk_en)
      #(T_wb_clk_period / 2) wb_clk = 1'b0;
  always@(negedge wb_clk)
    if (wb_clk_en)
      #(T_wb_clk_period / 2) wb_clk = 1'b1;


// SYSTEM signals tracker
//#######################

  // Reset
  always@(posedge wb_reset)
    -> reset_aserted;
  always@(negedge wb_reset)
    -> reset_released;

  // Interrupt
  always@(posedge wb_int_o)
    -> int_aserted;
  always@(negedge wb_int_o)
    -> int_released;


// UART register tracker
//######################

  // UART registers:
  //    ----------------
  //    RBR             (R/  | ADR 0 | DLAB 0)
  //      [7:0] -RX---- "rxdata" Receiver Buffer Register
  //    ----------------