wb_master_model.v

uart协议、实现、验证

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_master_model.v                                           ////
////                                                              ////
////  This file is part of the "uart16550" project                ////
////  http://www.opencores.org/projects/uart16550/                ////
////                                                              ////
////  Author(s):                                                  ////
////      - [e-mail] (Miha Dolenc)                     ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 authors                            ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// later version.                                               ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
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//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
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//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_master_model.v,v $
// Revision 1.1  2004/03/27 03:55:17  tadejm
// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.
//
//
//


`include "wb_model_defines.v"
`include "timescale.v"

module wb_master_model
(
    wb_rst_i    ,
    wb_clk_i    ,
    wbm_cyc_o   ,
    wbm_cti_o   ,
    wbm_bte_o   ,
    wbm_stb_o   ,
    wbm_we_o    ,
    wbm_adr_o   ,
    wbm_sel_o   ,
    wbm_dat_o   ,
    wbm_dat_i   ,
    wbm_ack_i   ,
    wbm_err_i   ,
    wbm_rty_i
);

// set the parameters to impossible values, so errors will be detected at compile time
parameter wb_dat_width  =   1   ;
parameter wb_adr_width  =   1   ;
parameter wb_sel_width  =   1   ;

real    Tperiod                 ;

input   wb_rst_i    ,
        wb_clk_i    ;

output  wbm_cyc_o   ;
reg     wbm_cyc_o   ;

output  [ 2: 0] wbm_cti_o   ;
reg     [ 2: 0] wbm_cti_o   ;

output  [ 1: 0] wbm_bte_o   ;
reg     [ 1: 0] wbm_bte_o   ;

output          wbm_stb_o   ;
reg             wbm_stb_o   ;

output          wbm_we_o    ;
reg             wbm_we_o    ;

output  [wb_adr_width - 1:0]    wbm_adr_o   ;
reg     [wb_adr_width - 1:0]    wbm_adr_o   ;

output  [wb_sel_width - 1:0]    wbm_sel_o   ;
reg     [wb_sel_width - 1:0]    wbm_sel_o   ;

output  [wb_dat_width - 1:0]    wbm_dat_o   ;
reg     [wb_dat_width - 1:0]    wbm_dat_o   ;

input   [wb_dat_width - 1:0]    wbm_dat_i   ;

input   wbm_ack_i   ;

input   wbm_err_i   ;

input   wbm_rty_i   ;

event write_transfer    ;
event read_transfer     ;

reg [wb_adr_width - 1:0] write_adr ;
reg [wb_sel_width - 1:0] write_sel ;
reg [wb_dat_width - 1:0] write_dat ;

reg [wb_adr_width - 1:0] read_adr ;
reg [wb_sel_width - 1:0] read_sel ;
reg [wb_dat_width - 1:0] read_dat ;

reg [wb_adr_width - 1:0] next_write_adr  ;
reg [wb_sel_width - 1:0] next_write_sel  ;
reg [wb_dat_width - 1:0] next_write_dat  ;
reg [ 2: 0]              next_write_cti  ;
reg [ 1: 0]              next_write_bte  ;

event write_accepted ;
event write_request  ;

reg [wb_adr_width - 1:0] next_read_adr  ;
reg [wb_sel_width - 1:0] next_read_sel  ;
reg [ 2: 0]              next_read_cti  ;
reg [ 1: 0]              next_read_bte  ;

event read_accepted                     ;
event read_request                      ;

real Tsetup ;
real Thold  ;

initial Tsetup = 0.0 ;
initial Thold  = 0.0 ;

reg reset_done  ;
initial reset_done = 1'b0 ;

event   error_event ;
reg     [ 799: 0] error_message ;

initial
fork
begin
    forever
    begin
        @(wb_rst_i) ;
        if ((wb_rst_i ^ wb_rst_i) !== 1'b0)
        begin
            reset_done = 1'b0   ;
            error_message = "Invalid WISHBONE reset line value detected" ;
            `WB_MODEL_ERR_MSG(error_message) ;
            -> error_event  ;
        end
    
        if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
        begin
            reset_done = 1'b0   ;
        end
    end
end
begin
    forever
    begin
        @(wb_rst_i) ;
        if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
        begin
            @(posedge wb_clk_i or wb_rst_i) ;
            if (wb_rst_i !== `WB_MODEL_RST_ACTIVE)
            begin
                error_message = "Reset de-activated prior to at least one positive clock transition" ;
                `WB_MODEL_ERR_MSG(error_message) ;
                -> error_event ;
            end
            else
            begin
                reset_done = 1'b1 ;
            end
        end            
    end
end
join

always@(wb_rst_i)
begin
    if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
        wbm_cyc_o <= 1'b0   ;
end

reg     access_in_progress          ;
initial access_in_progress = 1'b0   ;

task start_write ;
    input  `WBM_MODEL_WRITE_IN_TYPE    write_stim_i       ;
    output `WBM_MODEL_WRITE_OUT_TYPE   write_res_o        ;
    reg    [31: 0]                     num_of_slave_waits ;
    reg                                end_access         ;
begin:main

    write_res_o = 'h0 ;

    if (access_in_progress === 1'b1)
    begin
        error_message = "Task called when some other access was in progress" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event                   ;
        write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
        disable main    ;
    end

    if (reset_done !== 1'b1)
    begin
        error_message = "Task called before reset was applied to the design" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event                   ;
        write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
        disable main    ;
    end

    access_in_progress = 1'b1   ;
    end_access         = write_stim_i`WBM_MODEL_WRITE_LAST ;

    if (write_stim_i`WBM_MODEL_WRITE_FAST_B2B !== 1'b1)
        @(posedge wb_clk_i) ;

    wbm_cyc_o <= #(Tperiod - Tsetup) 1'b1 ;

    insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits)  ;

    if ((num_of_slave_waits ^ num_of_slave_waits) === 'h0)
    begin
        error_message = "Slave responded to initial write access" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event                   ;
    end

    num_of_slave_waits = 0          ;
    
    wbm_stb_o   <=  #(Tperiod - Tsetup) 1'b1            ;
    wbm_we_o    <=  #(Tperiod - Tsetup) 1'b1            ;
    wbm_adr_o   <=  #(Tperiod - Tsetup) next_write_adr  ;
    wbm_dat_o   <=  #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel)   ;
    wbm_sel_o   <=  #(Tperiod - Tsetup) next_write_sel  ;
    wbm_cti_o   <=  #(Tperiod - Tsetup) next_write_cti  ;
    wbm_bte_o   <=  #(Tperiod - Tsetup) next_write_bte  ;

    -> write_accepted ;

    @(posedge wb_clk_i) ;

    while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS))
    begin
        num_of_slave_waits = num_of_slave_waits + 1'b1  ;
        write_adr = wbm_adr_o ;
        write_sel = wbm_sel_o ;
        write_dat = wbm_dat_o ;
        -> write_request ;
        @(posedge wb_clk_i) ;
    end

    if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
    begin
        error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event  ;
        end_access = 1'b1   ;
        write_res_o`WBM_MODEL_WRITE_DESIGN_ERR   = 1'b1  ;
    end
    else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
    begin
        error_message = "Cycle terminated because invalid slave response was received" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event  ;
        end_access = 1'b1   ;
        write_res_o`WBM_MODEL_WRITE_DESIGN_ERR   = 1'b1  ;
    end
    else
    begin
        write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS  = num_of_slave_waits   ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_ACK    = wbm_ack_i            ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_ERR    = wbm_err_i            ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_RTY    = wbm_rty_i            ;

        if (wbm_ack_i === 1'b1)
        begin
            write_adr   =   wbm_adr_o  ;
            write_dat   =   wbm_dat_o  ;
            write_sel   =   wbm_sel_o  ;
            -> write_transfer   ;
        end
    end

    if (end_access)
    begin
        wbm_cyc_o   <= #(Thold) 1'b0 ;
        wbm_stb_o   <= #(Thold) 1'bx ;
        wbm_we_o    <= #(Thold) 1'bx ;
        wbm_sel_o   <= #(Thold) 'hx  ;
        wbm_adr_o   <= #(Thold) 'hx  ;
        wbm_dat_o   <= #(Thold) 'hx  ;
        wbm_cti_o   <= #(Thold) 'hx  ;
        wbm_bte_o   <= #(Thold) 'hx  ; 
        access_in_progress = 1'b0    ;
    end
end
endtask // start_write

task subsequent_write   ;
    input  `WBM_MODEL_WRITE_IN_TYPE    write_stim_i       ;
    output `WBM_MODEL_WRITE_OUT_TYPE   write_res_o        ;
    reg    [31: 0]                     num_of_slave_waits ;
    reg                                end_access         ;
begin:main

    write_res_o = 'h0 ;

    if (access_in_progress !== 1'b1)
    begin
        error_message = "Task called when no access was in progress" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event                   ;
        write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
        disable main    ;
    end

    end_access  = write_stim_i`WBM_MODEL_WRITE_LAST ;

    insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits)  ;

    if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0)
    begin
        num_of_slave_waits = write_stim_i`WBM_MODEL_WRITE_WAITS ;
    end
    
    wbm_stb_o   <=  #(Tperiod - Tsetup) 1'b1            ;
    wbm_we_o    <=  #(Tperiod - Tsetup) 1'b1            ;
    wbm_adr_o   <=  #(Tperiod - Tsetup) next_write_adr  ;
    wbm_dat_o   <=  #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel)   ;
    wbm_sel_o   <=  #(Tperiod - Tsetup) next_write_sel  ;
    wbm_cti_o   <=  #(Tperiod - Tsetup) next_write_cti  ;
    wbm_bte_o   <=  #(Tperiod - Tsetup) next_write_bte  ;

    -> write_accepted ;

    @(posedge wb_clk_i) ;

    while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS))
    begin
        num_of_slave_waits = num_of_slave_waits + 1'b1  ;
        write_adr = wbm_adr_o ;
        write_sel = wbm_sel_o ;
        write_dat = wbm_dat_o ;
        -> write_request ;
        @(posedge wb_clk_i) ;
    end

    if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
    begin
        error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event  ;
        end_access = 1'b1   ;
        write_res_o`WBM_MODEL_WRITE_DESIGN_ERR   = 1'b1  ;
    end
    else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
    begin
        error_message = "Cycle terminated because invalid slave response was received" ;
        `WB_MODEL_ERR_MSG(error_message) ;
        -> error_event  ;
        end_access = 1'b1   ;
        write_res_o`WBM_MODEL_WRITE_DESIGN_ERR   = 1'b1  ;
    end
    else
    begin
        write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS  = num_of_slave_waits   ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_ACK    = wbm_ack_i            ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_ERR    = wbm_err_i            ;
        write_res_o`WBM_MODEL_WRITE_SLAVE_RTY    = wbm_rty_i            ;

        if (wbm_ack_i === 1'b1)
        begin
            write_adr   =   wbm_adr_o  ;
            write_dat   =   wbm_dat_o  ;
            write_sel   =   wbm_sel_o  ;
            -> write_transfer   ;
        end
    end

    if (end_access)
    begin
        wbm_cyc_o   <= #(Thold) 1'b0 ;
        wbm_stb_o   <= #(Thold) 1'bx ;
        wbm_we_o    <= #(Thold) 1'bx ;
        wbm_sel_o   <= #(Thold) 'hx  ;
        wbm_adr_o   <= #(Thold) 'hx  ;
        wbm_dat_o   <= #(Thold) 'hx  ;
        wbm_cti_o   <= #(Thold) 'hx  ;
        wbm_bte_o   <= #(Thold) 'hx  ; 
        access_in_progress = 1'b0    ;
    end
end
endtask // subsequent_write

task start_read ;
    input  `WBM_MODEL_READ_IN_TYPE  read_stim_i         ;
    output `WBM_MODEL_READ_OUT_TYPE read_res_o          ;
    reg    [31: 0]                  num_of_slave_waits  ;
    reg                             end_access          ;
begin:main