led_8x8.map.rpt

取用Verilog语言驱动一个8*8点阵形。

; lpm_constant.inc                 ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal80.inc                    ; yes             ; Megafunction           ; c:/altera/80/quartus/libraries/megafunctions/aglobal80.inc           ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+----------------------+----------------------------------+
; Resource             ; Usage                            ;
+----------------------+----------------------------------+
; Logic cells          ; 50                               ;
; Total registers      ; 27                               ;
; I/O pins             ; 17                               ;
; Parallel expanders   ; 7                                ;
; Maximum fan-out node ; lpm_counter:count_rtl_0|dffs[13] ;
; Maximum fan-out      ; 36                               ;
; Total fan-out        ; 509                              ;
; Average fan-out      ; 7.60                             ;
+----------------------+----------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                ;
+------------------------------+------------+------+----------------------------------+--------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name              ; Library Name ;
+------------------------------+------------+------+----------------------------------+--------------+
; |led_8X8                     ; 50         ; 17   ; |led_8X8                         ; work         ;
;    |lpm_counter:count_rtl_0| ; 27         ; 0    ; |led_8X8|lpm_counter:count_rtl_0 ; work         ;
+------------------------------+------------+------+----------------------------------+--------------+


+------------------------------------------------+
; Source assignments for lpm_counter:count_rtl_0 ;
+---------------------------+-------+------+-----+
; Assignment                ; Value ; From ; To  ;
+---------------------------+-------+------+-----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -   ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -   ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -   ;
+---------------------------+-------+------+-----+


+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:count_rtl_0 ;
+------------------------+-------------------+-----------------------------+
; Parameter Name         ; Value             ; Type                        ;
+------------------------+-------------------+-----------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                  ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE              ;
; LPM_WIDTH              ; 27                ; Untyped                     ;
; LPM_DIRECTION          ; UP                ; Untyped                     ;
; LPM_MODULUS            ; 0                 ; Untyped                     ;
; LPM_AVALUE             ; UNUSED            ; Untyped                     ;
; LPM_SVALUE             ; UNUSED            ; Untyped                     ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                     ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                     ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                     ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH          ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK          ;
; CARRY_CNT_EN           ; SMART             ; Untyped                     ;
; LABWIDE_SCLR           ; ON                ; Untyped                     ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                     ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                     ;
+------------------------+-------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Sun Mar 08 13:53:24 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_8X8 -c led_8X8
Info: Found 1 design units, including 1 entities, in source file led_8X8.v
    Info: Found entity 1: led_8X8
Info: Elaborating entity "led_8X8" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at led_8X8.v(24): truncated value with size 32 to match size of target (27)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=27) from the following logic: "count[0]~0"
Info: Elaborated megafunction instantiation "lpm_counter:count_rtl_0"
Info: Instantiated megafunction "lpm_counter:count_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "27"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 67 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 16 output pins
    Info: Implemented 50 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 152 megabytes
    Info: Processing ended: Sun Mar 08 13:53:27 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03